Modeling and testing for signal integrity in nanometer system-on-chips

Shrinking feature sizes, blistering clock speeds and ever-increasing integration capability have fueled the fast evolution of the semiconductor industry and led to the emergence of System-on-Chips (SoCs). SoCs feature various components integrated onto a single chip, thus enabling higher performance and lower power consumption than discrete integrated circuits (ICs). However, many previously negligible noise effects are becoming prominent and frequently causing failures in nanometer SoCs. Noise caused by coupling capacitance together with random defects and large process variations can have a significant adverse impact on the performance and error-free operation of nanometer SoCs.; Signal Integrity (SI) problems are becoming critical and cannot be safely masked by simple design rules anymore. Combining the paradigms of design and testing for signal integrity, this dissertation presents research contributions on the topic of modeling and testing for crosstalk noise and crosstalk-induced AC failures (crosstalk errors) on global interconnects and local wires in SoCs. The contributions of this thesis include: (I) Fault modeling and at-speed testing for crosstalk errors on system-level interconnects; (II) A fast yet accurate static noise analysis technique; (III) Automatic test generation methodologies for crosstalk errors on local interconnects using design-for-test (DFT) techniques and programmable on-chip resources. We successfully validated these methodologies on several benchmark circuits and industrial designs. The proposed methodologies enable low-cost, at-speed testing for crosstalk errors in processors and SoCs.