High-performance techniques for digit-serial applications and LDPC codes

Design techniques can be used to increase the performance of digital systems. This thesis introduces several design innovations that load to better performance than previous approaches.; In the first technique, digit-serial design is mapped onto skew-tolerant domino circuits. In this design methodology, a digit size of N bits is efficiently mapped onto an N-phase overlapping clocking scheme, so that N bits are processed during each full clock cycle.; In the second innovation, an efficient simulation methodology is presented for modeling the time borrowing behavior of skew-tolerant domino circuits.; The above design methodologies are evaluated in several important applications. Specifically, a 512-bit modular multiplier, a 16-bit unsigned multiplier, a 16-bit signed multiplier, and an 8-tap FIR filler have been designed and simulated. Comparative results show the effectiveness of the proposed design methodologies.; Finally, various styles of implementation for Low Density Parity Check (LDPC) codes are developed. We describe a rapid design methodology which automatically generates structural VHDL code for Field Programmable Gate Arrays (FPGAs) using MATLAB. To demonstrate this design methodology, an LDPC encoder and decoder are constructed on a Xilinx Virtex-II device with various block sizes and a code rate of 1/2. An evaluation of the hardware cost and data throughput is given and simulations results for the bit error rate (BER) are obtained as a function of block size.