Voltage scaling constraints for static CMOS logic and memory circuits

Scaling the supply voltage (V_dd) for logic and memory circuits is widely accepted as the most effective way to lower Complementary Metal Oxide Semiconductor (CMOS) system power dissipation and power density as this lowers all components of total power dissipation and is felt globally across the entire system. Signal quantization requirements for logic operations and data storage, nonscalability of the band-gap energy of silicon, increasingly severe atomic fluctuations, exponentially increasing subthreshold leakage, higher local clock rates, larger delay variations due to device and interconnect process variations and increasing voltage drops across the power distribution network limit the scalability of CMOS system voltages. These limitations place bounds on reductions in the power dissipation, reliability and cost of conventional CMOS systems mandating an investigation on these limits and the development of innovative solutions to circumvent these limitations. This thesis proposes new models and methodologies to codify the constraints on scaling supply voltage across the (i) fundamental, (ii) material, (iii) device, (iv) circuit and (v) system levels of a hierarchy of limits for digital CMOS systems. The voltage scaling constraints quantified in this thesis will permit designers to understand the lower bounds on supply voltage scaling and also reveal opportunities for innovative circuit techniques to reduce total system power drain.