Techniques for high-level testability analysis and optimization

This thesis presents a suite of techniques to automatically perform testability analysis and optimization for designs at the register-transfer and system levels of the design hierarchy. It is only recently that test generation has moved to the register-transfer level (RTL). We use the algebra of regular expressions to formulate a unified test framework called TAO for testing RTL controller/datapath circuits of ASICs, application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs) and microprocessors. Since it is highly desirable that a test generation framework not only identify testable and untestable portions of a circuit but also come up with suitable test hardware suggestions to make the circuit more testable, we also augment TAO with a design-for-test (DFT) framework. Our DFT engine can provide a low-cost test insertion solution by examining trade-offs in area and delay while choosing from a diverse array of testability modifications. These DFT modifications include choices of partial scan or test multiplexer insertion in different parts of the circuit. We also show that the testability analysis framework and DFT engine can be easily tailored to make judicious test insertion choices for generating self-testable designs.; One of the main components of the manufacturing test costs is the capital investment for automatic test equipment or testers which are used to actually apply the tests. Since high test application time means high test costs, it becomes important to reduce the test application time associated with the generated tests. Hitherto, high-level ATPG techniques have not considered the possibility of reducing test application time during the course of test generation. We provide a series of RTL test compaction techniques that fill this void. Our test compaction techniques advance the ideas of test parallelization and test pipelining to reduce test application time significantly.; The design paradigm of using embedded cores to provide system-on-a-chip (SOC) solutions has become a critical component of today's computing technology. Therefore, a test engineer now has the additional responsibility of performing system-level test generation. Our work provides a comprehensive framework that generates low-overhead compact test solutions for SOCs. (Abstract shortened by UMI.)...