Massively parallel reconfigurable architecture and programming for wireless communications

The field of wireless communications is witnessing an explosive growth, stimulated by emerging applications such as 3G wireless systems and mobile Internet telephony. While most of the wireless traffic has been provided by voice communications, we are observing a shift to data applications with unknown requirements. New standards for wireless cellular are being rolled out, that promise data rates from 384 kbits/sec up to 2 Mbits/sec. By looking at the future, we could imagine a mobile “phone” that runs high performance video applications through a high speed connection to the Internet, and being able to reconfigure itself to work properly inside both a cellular and Wireless LAN environment. The basic trend in these mobile devices will be high bit-rates.; The quest for ever higher bit-rates cannot be satisfied by only increasing the speed of the underlying DSP that implements the particular wireless standard. Owing to the fact that the wireless spectrum is a shared resource, the wireless communication designers are challenged to jam more bits into a narrower band, or to increase the capacity of the wireless channel in bits/sec/Hz/Joule. It is well known that the capacity of the current wireless systems is well below the theoretical limit offered by Shannon's theorem. Wireless channel capacity and spectrum efficiency call for the design of advanced communication algorithms. Techniques such as: beamforming, multi-antenna diversity, multiuser detection and interference cancellation, can provide a dramatic increase in spectral efficiency. Doing so requires extensive signal processing and vast increase in computational requirements that rise faster than what is offered by Moore's law for micro-processors.; In this thesis we propose a massively parallel reconfigurable processor architecture targeted for the implementation of advanced communication algorithms featuring a large number of matrix computations. We believe that any novelty in the area of parallel reconfigurable computing should have an impact on the way we program the architecture. To this end, we developed a C++ compiler that allows the communication engineer to design an algorithm in a high level language like MATLAB. The MATLAB code is compiled to a configured executable architecture described as a Simulink model. We provide design examples that demonstrate a 2–3 orders of magnitude difference in energy efficiency between the proposed architecture and a state of the art DSP processor. (Abstract shortened by UMI.)...