Low-voltage radio-frequency CMOS integrated circuits in silicon-on-insulator

This thesis examines the advantages of silicon-on-insulator (SOI) CMOS for low-voltage radio-frequency (RF) application. It explores the unique properties of SOI transistors, exploiting these properties to construct RF circuits with better performance (such as higher speed lower noise) compared to bulk CMOS. The cross-coupled complementary voltage-controlled oscillator (VCO) was chosen as the baseline circuit for the comparison.; First, a wideband VCO using AMOS varactors with more than 50% tuning range was implemented, demonstrating the low-voltage frequency tuning capability in CMOS. Next, a 40 GHz VCO using both PMOS and NMOS was constructed to illustrate the high speed performance of SOI CMOS transistors. High-speed design issues, especially regarding frequency tuning capability, have been studied and analyzed. While AMOS varactors make low-voltage tuning in CMOS possible, the high varactor sensivity introduces excessive phase noise into the system. This thesis explores and analyzes this noise problem. Two design methodologies, namely band-switching and differential tuning, were employed to reduce such noise. Furthermore, a general phase noise improvement technique, which can be applied to both SOI and bulk CMOS VCOs, was also developed and demonstrated. This technique utilizes the complementary topology to reduce upconversion flicker noise, while using the non-minimum gate length NMOS devices to maximize signal swing and reduce transistor noise. All the VCOs described above are implemented in a 0.13 μm SOI CMOS technology, and the theories developed were verified experimentally by these RF circuits.; Finally, several high-speed low-voltage circuits are either simulated or implemented to demonstrate the improved circuit performance available with SOI: (a) a bias-T source follower for accurate high-speed VCO measurement; (b) a 5.4 GHz low-noise amplifier with image reject using high-Q passives, giving zero do power dissipation for the image reject circuit; (c) a 1 V, 40 μW, 50 MHz. 6-bit, ΔΣ analog-to-digital converter (ADC) to demonstrate low-voltage switched-C performance; and (d) a 1 V, 5 GHz, 3-bit pipeline ADC used as a multi-bit quantizer for future ΔΣ bandpass ADC implementation.