Synthesis of high-performance self-checking delay-insensitive tree circuits

Circuits may be classified as synchronous or asynchronous. Synchronous circuits have a clock to synchronize the operations of subsystems while asynchronous circuits do not. Subsystems in asynchronous circuits usually need start and completion mechanisms to synchronize with one another. Because of the potential advantages of asynchronous design--no clock skew problem, low power consumption, average-case performance, modularity, composability and reusability--interest in asynchronous logic design is increasing.;The promise of high performance is especially attractive. To achieve high performance, one must design a fast self-timed circuit with good average case performance and a fast completion detection circuit, detecting the completion of the self-timed circuit.;This thesis presents several novel designs of fast and robust delay-insensitive or self-timed components, such as high performance delay-insensitive carry lookahead adders, high performance delay-insensitive Brent & Kung adders, completion detection circuits and high performance delay-insensitive tree comparators, as well as a general and novel methodology for synthesis of high speed, totally self-checking, delay-insensitive iterative tree circuits.;The goals of the thesis are: (1) to synthesize high performance data-dependent delay-insensitive circuits which may operate at average rate and high performance completion detection circuits which minimize the overhead entailed in self-timed systems; (2) to design robust hardware components serving as building blocks which may be used to build complex systems just like those software objects, and (3) to design self-checking circuits which may detect malfunctions in normal operation.