Built-in self-test and fault simulation for analog/mixed-signal circuits

Analog/mixed-signal ICs have enjoyed tremendous demands in various applications. However, development of high quality, low cost tests for analog/ mixed-signal ICs remains a difficult task. On one hand, test methodologies need to consider various sources of costs including test quality, test equipments and test application time. On the other hand, the simulation cost in developing such methodologies could be non-trivial.; In this thesis, we present new test methodologies and fault simulation methods for analog/mixed-signal ICs. Both fault-model-driven and specification-driven techniques and their Built-In Self-Test (BIST) implementations for modern analog/mixed-signal ICs are addressed. In fault-model-driven testing, we use fault coverage based on catastrophic and parametric faults as the quality measure. In specification-driven testing, we attempt to minimize percentage of misclassification for device under tests (DUTs) subject to processing disturbance. Requirements of test hardware and test application time for the proposed tests are also discussed.; In fault simulation, we address both macromodel-based and partition-based methods. We propose new fault macromodeling technique which is formulated as a parameter mapping problem. Such a mapping is based on evaluation of functions interpolated by empirical data. In the partition-based method, only a small number of building blocks, instead of the entire chip, is fault simulated. In particular, we use a real industrial design to demonstrate the effectiveness and efficiency of the partition-based fault simulation method.