Behavioral synthesis for application-specific programmable DSP systems

The behavioral synthesis design methodology has been developed to deal with the growing complexity of designing digital systems. Previous research in the behavioral synthesis of real-time DSP systems has focused on the development of custom, dedicated hardware or embedded software for general purpose DSP microprocessors. This research investigates the application of behavioral synthesis to programmable, application specific DSP cores. The architecture developed for these DSP cores is called Field Programmable DSP Arrays (FPDA). The FPDA architecture can be customized to meet the requirements of the a specific application area, by designing the processor using application specific execution units. The FPDA architecture is programmed using a microcode program. This architecture allows FPDA processors to be included as part of a Application Specific Integrated Circuit (ASIC), or developed as a programmable DSP component. Multi-processor extensions to the basic FPDA architecture are provided, for applications that require additional processing power.;The VDFL behavioral specification language has been developed as the input language for FPDA synthesis. VDFL provides a specification language with language constructs which closely match the characteristics of DSP algorithms. The Wizard behavioral synthesis tool has been developed to synthesize a VDFL specification into a microcode program for the FPDA architecture. Wizard is designed as an extendible synthesis tool, in order to allow new FPDA processor architectures to be added to the design flow. The FPDA target architectures supported by Wizard include: custom, single-processor, and multi-processor systems. The microcode produced by Wizard can be simulated on a behavioral model of the FPDA processor system. After the implementation of programmable FPDA processors, the microcode could be loaded to an evaluation board for a real-time evaluation of the synthesized system.