Mitigation of Variability and Reliability Margins in IC Implementation

In the late-CMOS era, system-on-chip design and manufacturing margins continue to increase in light of process variability, circuit reliability and wide operating conditions. Despite continuing enhancements to both manufacturing and design technologies, substantial IC product value in terms of manufacturing yield, circuit area and power, and design turnaround time is left on the table due to conservatism in the design and manufacturing flows. These margins are now extremely costly, as the benefits from deployment of the next technology node are now only approximately 20% in circuit performance, power and density. To reduce margins, accurate modeling and assessment of the impacts of variability and reliability are essential. Meanwhile. innovative manufacturing and design techniques must be developed based on a comprehensive understanding of the benefits and costs of such new measures. This thesis presents new techniques to mitigate variability and reliability margins in leading-edge SoC design and manufacturing. These techniques can be grouped into three main thrusts: (i) design for manufacturability and reliability; (ii) signoff condition optimization; and (ill) design-aware manufacturing optimization.;In the design for manufacturability and variability thrust, this thesis presents two performance sensor designs for adaptive voltage scaling, which can be used to mitigate the impact of process variations. To reduce design margins for time-dependent dielectric breakdown reliability, this thesis presents a layout optimization technique and a design-dependent reliability analysis framework.;In the signoff condition optimization thrust, this thesis presents analyses of the design overheads due to suboptimal signoff conditions with respect to (i) circuit operating voltage and performance; (ii) modeling of timing impacts of circuit aging; and (iii) corner models of wire parasitic resistance and capacitance. Tradeoffs between design quality and signoff margins, as well as methods to optimize signoff conditions, are also addressed.;In the design-aware manufacturing optimization thrust, this thesis presents three distinct techniques to improve manufacturing yield by considering the impact of manufacturing variations on the design's timing and leakage power. First, the electrical process window provides a more accurate method to quantify the impact of lithographic variability on circuit performance and leakage. Second, design-dependent monitoring provides a cost-effective way to estimate circuit parametric yield based on test structures deployable in the early stages of a manufacturing flow. Finally, analysis of the impact of overlay error in double-patterning lithography provides guidelines to reduce circuit performance variation.