Analysis of data compression and re-computation in multi-core embedded architectures

In recent years, multi-core architectures with software-managed memory components are widely used in embedded systems. Due to its advantages over hardware-controlled counterparts software-managed memory such as scratch-pad memory (SPM) is preferred by embedded system designers to optimize various design metrics such as performance, power consumption, and memory space consumption. In this thesis, we presents an approach to improve performance of multi-core embedded architectures utilizing on-chip software-managed memory at two hierarchy levels with different memory access latencies. The proposed approach targets at data-intensive applications and decreases the execution time of such applications by reducing the number of off-chip accesses. The off-chip memory accesses are reduced using two techniques: data compression and data re-computation. Data compression is performed to increase the amount of on-chip data. Data re-computation is done by re-computing the value of an off-chip data element using on-chip data elements instead of making an off-chip memory access.;The target architecture used in this work is a four-core embedded architecture. Each core has a local SPM; and each core accesses other SPMs (remote SPM) with higher memory access latency. Software-managed on-chip L2 memory is shared by all cores and divided into two portions: the first portion holds the data in compressed form and the second portion holds the data in uncompressed (regular) form. Off-chip memory is used by all cores and holds the entire dataset.;In the proposed approach, after profiling the embedded application, the dataset is divided into blocks and the block access frequencies are calculated. Based on the access frequencies and the size of on-chip memory components the data is mapped to on-chip SPMs, software-managed on-chip L2 and off-chip memory. More specifically, the blocks with highest access frequencies are mapped to local SPMs and the first portion of L2; moderately accessed blocks are mapped to the second L2 in compressed form; and, the off-chip memory holds all dataset. Then, possible re-computation opportunities in the program code are investigated. The re-computations that help improving performance are implemented and program code is modified accordingly. The experimental results collected using various benchmark programs show the viability of the proposed approach.