| This thesis describes the architecture design of the SE (Surface Evaluation) chip, a VLSI chip dedicated to the B-spline surface evaluation, which can be used toease the Computer-Aided Geometric Design (CAGD) of B-spline surfaces. The reconfigurable structure of the SE chip can perform on-chip blending function formulation and high-speed vector-matrix multiplication at less hardware cost. Pipelining and parallel processing techniques are applied to the inter- and intra-functional unit designs to speed up the calculation of the surface evaluation algorithm. The symbolic example and the description of the SE chip written in RTL (Register Transfer Language) verify the correctness of the design. Area estimation confirms the feasibility of a semi-custom implementation approach with current technology and speed estimation shows at least an order of magnitude improvement over existing graphics hardware in performing surface evaluation. The SE chip architecture can also be used to execute the coordinate transformation, tangent and normal vector derivation, and shading. |
