MULTI-LEVEL LOGIC ARRAY SYNTHESIS (MINIMIZATION, VLSI DESIGN, WEINBERGER, DESIGN AUTOMATION)

Automatic synthesis of VLSI circuits from function descriptions creates the opportunity for vastly reduced design cost, but presents formidable challenges. This silicon compilation can be accomplished by a four step translation: (1) writing the function in terms of available logic components, (2) minimization of this logic representation, (3) mapping of logic into the target technology's circuit primitives, and (4) selection of a detailed layout configuration. Existing methods based on programmable logic array (PLA), standard cell and gate array topologies attack the problem using restrictions on logic minimization or circuit topology. A new method based on multi-level logic and Weinberger arrays integrates the entire compilation from functional description to layout generation, and provides greater flexibility in logic minimization, circuit topology and design goals. Multi-level logic and Weinberger arrays serve as ideal partners in synthesis of large circuit structures. Deeply nested logic expressions can save area, power, and circuit delay compared to their more common sum-of-products equivalents, and Weinberger arrays can directly implement the arbitrary interconnections required by these complex logic functions. The Stanford Weinberger Array Minimizer and Implementor (SWAMI) system explores two phases of this compilation with special care, heuristic minimization of multi-level logic expressions, and gate placement in Weinberger arrays.; SWAMI's logical optimization phase adopts heuristic methods to reduce the circuit area and delay for each logic function. Three transformations, decomposition, composition and local rewriting, change the depth of the logic representation and capitalize on commonly used subexpressions. The topological optimization phase presents new algorithms for linear ordering placement in one-dimensional Weinberger arrays, and introduces a new topology for two-dimensional logic arrays. SWAMI tunes nMOS and CMOS layouts for area and performance according to designer specifications, and produces VLSI logic blocks that are often smaller or faster that equivalent PLA-based implementations.