| Based on the directed graph theory,this paper researches the automated testing method for the interconnection resources of the SRAM FPGA with the object of Virtes-5 series FPGA of Xilinx.Aimed at less test time or test times as possible to complete coverage testing of interconnection resources as much as possible,so as to shorten the test time of chip factory,reduce test cost.This paper researches mainly like this:1)First analyze the structure and line type of the metal interconnects in the FPGA,and divide the resources such as double lines,pentagonal lines and long lines.Then the structure of the switch matrix in the FPGA is analyzed,and the driving relationship between the PIPs inside the switch matrix is obtained.2)According to the directed graph theory,the double line,the pentagonal line,the long line,the switch matrix and their ports in the interconnected resources,including the structure of the CLB can be abstracted mathematically.So the graph model of each part is obtained respectively,and then they are merged to obtain a graph model of the overall interconnected resources.3)The search algorithm of the test path is researched on the basis of the interconnected resource graph model.It is proposed that improve and combine the network maximum flow algorithm and the breadth-first search algorithm,and obtain the test paths in the horizontal,vertical and two oblique directions respectively.Then design the test vector,and test interconnection resources on the test machine.Finally,the test results are statistically analyzed.Through above research,test and analysis,it can be concluded that the test method in this research can reduce the test time of interconnection of XCV series FPGA by 33%,and cover 96% interconnection resources of Virtes-5series FPGA under test with configuration in 18 times,costing 4.66 seconds.It is obvious that it shorten test time with high test coverage,which meets the engineering requirement and the expection of this research. |
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