| China is one of the countries with a large amount of geological resources reserves,but it has little advantage in resource utilization rate,mainly due to the difficulty of investigating resources and energy investigation and the high requirements of technology and equipment.At present,the mainstream data survey nodes mainly adopt the distributed seismic exploration data synchronous collection technology,which can realize the large-range geological data collection of complex terrain.The domestic distributed data collection system is still mainly wired distributed collection,with deployment difficulty and high cost.With the development of wireless communication technology,the advantages of wireless distributed data acquisition system,with simple deployment and long transmission distance.The difficulty of the wireless distributed collection system is the synchronization of data collection and the real-time nature of data transmission.The performance of the synchronization algorithm determines the accuracy of the collection system,directly affects the power consumption index and the availability of the system.In this paper,new clock tame circuit for distributed multi-node synchronous acquisition technology,and the two design schemes are optimized with high synchronization accuracy and low power consumption and can be suitable for seismic exploration synchronous acquisition system.The thesis first analyzes clock synchronization technology and obtains two optimized clock synchronization design schemes: one is to tame the constant static pressure controlled oscillator based on PID digital phase lock loop to stabilize the output of high-precision clock.The design uses TDC technology to detect the local clock and GPS second pulse,make frequency error estimation through least squares fitting,and then transforms the frequency error signal to thermostatic crystal oscillator through PID control algorithm to realize clock synchronization.The second is the high-precision synchronization clock scheme based on FPGA phase locking loop tame clock.This scheme uses dynamic reconfiguration technology that the digital phase locking loop has self-consistent closed loop function,improves the structure model of loop filter and pressure controlled oscillator,and uses the proportional integrated control filter with the dynamic configuration strategy,improving the quality of the oscillating signal and the locking speed of the phase-locked loop.The clock signal generated by this design not only has a small cumulative error and a random error,but also the control word of the oscillator can be dynamically configured according to the historical data to output a stable high-precision clock,greatly reducing the GPS continuous working time.In specific implementation,this design adopts STM32L4 series low power consumption MCU as the main control chip,performs low power consumption optimization design of the circuit,and performs dynamic low power consumption adaptation of the software according to the system configuration.In terms of synchronous acquisition,the tame high-precision clock signal is used as the external reference signal of the controller,and the data synchronous acquisition is controlled through software synchronization.The communication mode of narrow band and broadband is adopted to realize the real-time data return transmission,and to consider the low power consumption characteristics of the system.In terms of long-distance node communication,Lo Ra-based communication mechanism and data transmission using 4G/5G communication for real-time data.In terms of system stability,the power management circuit is designed to realize the anti-interference of the power supply noise and the circuit protection,and to ensure the smooth operation of the system.Finally final construction. |
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