Design On Statistical Model And Low Probability Evaluation Method Of Low Voltage Storage Circuit

With the continuous development of the semiconductor industry,especially in low-voltage scenarios,the impact of process variation on integrated circuits is becoming more and more serious,especially SRAM circuits composed of tens of millions of repeating cells.SRAM cells must have extremely low failure rates to ensure the yield requirements.For the rare probability events,traditional statistical methods are faced with the problem of too many simulation times,while some advanced importance-based sampling methods,such as HDIS algorithm and AIS algorithm,the former still need tens of thousands of simulation times,and the accuracy and speed of the latter algorithm are greatly affected by the predefined variance of the sampling function.Therefore,the development of a new rapid yield analysis method is particularly important.In order to solve the above problems,a Scaled-Sigma Adaptive Importance Sampling(SSAIS)algorithm based on High Dimensional Model Representation(HDMR),referred to as HAIS algorithm is proposed.The first is the SSAIS algorithm to reduce the number of simulations not only changes the position of the sampling function distribution through resampling based on AIS,but also dynamically changes its variance using the EM(Expectation-maximization)algorithm.In order to reduce the extra simulation time required to change the variance as much as possible,the entire iteration process is divided into several batches,which contains a small number of iterations,and the variance is changed after the iterations of each batch.The second is the Gaussian ProcessHigh Dimensional Model Representation(GP-HDMR)to reduce the circuit simulation overhead,where the establishment of the high-dimensional model is decomposed into the sum of the lowdimensional models.For the variables that have a linear relationship with the circuit performance,the linear basis function is fitted.For the variables that have a nonlinear relationship with the circuit performance,the Gaussian process basis function is fitted.Embed the trained model into the weight calculation part in the SSAIS algorithm to replace the HSPICE circuit simulation,achieving the purpose of further accelerating the yield evaluation speed on the basis of the SSAIS algorithm.The performance of proposed algorithm is verified by SRAM cell and SRAM arrays in SMIC40 nm process,1.0V and 0.6V low voltage scenarios.The accuracy of the algorithms are compared with Monte Carlo known as the “gold standard”.Not only in the 1.0V but also the 0.6V low voltage scenarios,the accuracy of the HAIS algorithm is much higher than that of the HDIS algorithm and the AIS algorithm.When the voltage is 1.0V,for the SRAM cell,the speed of HAIS is improved by3.8 times and 1.8 times compared to the HDIS algorithm and AIS algorithm respectively;for SRAM arrays,the speed of the proposed is improved by 5.1 times and 2.5 times compared to the HDIS algorithm and AIS algorithm respectively.At 0.6V,for SRAM cells,the speed is improved by 5.5times and 2.5 times compared to the HDIS algorithm and AIS algorithm respectively;for SRAM arrays,the speed is improved by 5.0 times and 2.9 times compared to the HDIS algorithm and AIS algorithm respectively.