Design And Implementation Of High Speed And High Precision Matrix Inverter

With the development of technology and application requirements,a large number of high-precision floating-point operations are involved in neural networks,digital signal processing,wireless communication technology and other fields.As a basic operation of signal processing,matrix operation is widely used in various fields.The inverse operation is the most complex and core operation in matrix operations.The traditional inverse algorithm is not suitable for hardware implementation because of the high complexity of the operation and the complicated process.Therefore,a large number of research teams at home and abroad have proposed a series of methods for matrix inversion,and verified and implemented them in hardware.The complexity of matrix inverse operation is proportional to the order cubic,so most of the existing matrix inverters are for special matrices or small-scale matrices based on fixed points.Therefore,it is very important to design a hardware matrix inverter for high precision and high dimensionality to explore the architectural significance and practical engineering value.In summary,this thesis carries out the following main work based on an in-depth study of existing matrix inversion algorithms and hardware implementation architectures:(1)The existing matrix inversion algorithm is analyzed and explored,and the matrix decomposition algorithm based on Column-wise Givens Rotation(CGR)decomposition method with in-situ substitution and chunking is selected based on the complexity of the algorithm itself,the complexity of hardware implementation and numerical stability,etc.The inverse upper triangular matrix inversion method is used to give full play to the parallel characteristics of the algorithm and ensure that the actual circuit performance meets the expected target.(2)According to the characteristics of the CGR algorithm,a hardware gas pedal for matrix inversion operation is designed to accelerate the inversion of double-precision floating-point square arrays.In the QR decomposition process of the matrix,the two-dimensional pulse array structure is optimized and a one-dimensional linear structure is designed,which gives full play to the characteristics of the flowing computation process of the CGR algorithm and compresses the operation cycle in the decomposition process.(3)The simulation verification,comprehensive implementation,back-end optimization and layout implementation are completed according to the standard ASCI flow,and finally the verification environment is built and verified on the Xlinx XC7V440T FPGA platform.The experimental results show that the matrix inverter designed in this paper can support any double-precision floating-point matrix inverse operation of order 2-32,and under the TSMC 28nm process,the inverter supports an operating frequency of700MHz and a chip area of 1.08mm²,and can complete the 32-order double-precision floating-point matrix inverse operation in 14123 cycles.The average relative error between the calculation results and MATLAB is below 10^-8,and its performance is 40times that of an AMD Ryzen 5 3500U CPU after frequency normalization and 118 times that of an NVIDIA RTX3070 GPU after area normalization.