Research On FPGA-based Real-time FFT Analysis

The efficient and fast implementation of Fast Fourier Transform(FFT)to Discrete Fourier Transform(DFT)has promoted the development of digital signal processing technology.With the development of high-frequency signals,high-speed sampling of different signals to obtain more accurate analysis results has become the focus of attention.Therefore,the number of sampling points covers a certain range of large-point FFT analysis,which has attracted wide attention in the high real-time application scenarios of embedded edge computing.Although FFT reduces the computational complexity of DFT,large-point FFT processing has a large amount of data and many computation steps.The FFT algorithm based on a large number of the same complex multiplication and addition as the basic unit is difficult to fully expand the computations in the sequential processing general-purpose processor.Low efficiency and prolonged computing time affect the real-time performance of signal analysis.In view of this,this thesis conducts research on the real-time processing of large-point FFT at the embedded edge,and proposes a custom FFT calculation acceleration unit design method based on Field Programmable Gate Array(FPGA).First,a pipelined FFT computing architecture with configurable butterfly operation stages is designed for embedded big data stream application scenarios.On this basis,Optimize FFT storage resources by using Coordinate Rotation Digital Computer(CORDIC)and step-by-step adjustment of bit width,and verify on the designed FFT real-time processing platform.The specific research content is as follows:(1)Aiming at the problem that the variable FFT that covers the processing of large points is difficult to be processed in real-time on a general-purpose processor,a pipelined FFT computing architecture with configurable butterfly operation stages based on FPGA is designed.This architecture combines the characteristics of FFT computing,adopts the feedback delay method to pipeline processing the input data,and uses the time parallel computing method to improve the computing efficiency of FFT.At the same time,the number of FFT computing points is changed by increasing or reducing the number of butterfly operation stages,which improves the flexibility of adapting to different FFT computing points application scenarios.The experimental results show that the architecture can realize the real-time processing of FFT with variable number of points and the computation result is correct.(2)Aiming at the problem of resource shortage caused by the deployment of large-point FFT with limited on-chip storage in the FPGA,a self-generated data bit-width variable butterfly operation architecture of the twiddle factor is designed to optimize resources.Combining the CORDIC algorithm and the symmetry of the rotation factor,the rotation factor is computed in real time to reduce the storage resource consumption caused by a large number of storage rotation factors.Combined with the characteristics of the pipeline FFT computing architecture,the method of adjusting the data bit width step by step is adopted to reduce the computing and storage resources required for FFT processing.The experimental results show that the real-time computation of the twiddle factor and the step-by-step adjustment of the data width using the CORDIC algorithm can effectively reduce the consumption of FFT storage resources while ensuring the computation accuracy.(3)In response to the application requirements of data transmission and computing task scheduling in the deployment of large-point FFT real-time processing at the edge,a heterogeneous So C architecture processor is used to build an FFT real-time processing system.According to the actual requirements of data transmission,buffering and calculation in the FFT real-time processing,the hardware platform is designed.And the corresponding firmware and software are designed based on this to complete the work flow of FFT real-time processing.Finally,the FFT real-time processing system designed in this paper is carried out verification.The test results show that The FFT real-time processing system constructed in this paper has achieved real-time processing of189.572 ?s for 16k-point FFT computing under 4.18 W power consumption.