Research On Single Event Effect Based On Circuit Level Simulation

There are a lot of high-energy particles in the universe,which can cause single event effect when bombarding semiconductor devices,resulting in function errors.According to whether this error causes permanent damage,it can be divided into hard errors and soft errors.Soft errors can be divided into single-event flip and single-event transient according to the different effects of particles on devices.The research on soft errors can be divided into single-event effect modeling and soft error prediction modeling for circuits.At present,the widely used single-event effect models are mostly device-level models and circuit-level models.Device-level models are more accurate but timeconsuming,while circuit-level models have higher simulation speed.However,with the development of semiconductor technology,the accuracy is gradually decreasing.To build a single event effect model compatible with accuracy and speed has become the focus of researchers around the world.At the same time,most of the existing prediction models of combinatorial logic soft errors are based on the assumption that the logic gates being bombarded have the same pulse width.However,in the actual radiation environment,different basic gates have different pulse widths with the same Linear energy transfer(LET).In view of the above problems,this thesis has done the following work:1.In this thesis,the device modeling of NMOS was carried out using 40 nm process,and the device was calibrated by adjusting the device doping concentration and device structure.Then,on the basis of this device model,the device-circuit level hybrid simulation of the SRAM was carried out,and the effects of the incident distance and LET on the single-event transient current of the sequential devices were analyzed to provide theoretical and data support for the subsequent study.Based on the above study,a machine learning approach was used to model the single-event transient current,with the incident distance and LET as well as the simulation time as inputs and the SET current as outputs,and a machine learning-based single-event transient current model was constructed.The prediction results were compared with the device-circuit level simulation results with an accuracy of over 91%,thus verifying the correctness of the model.2.In this thesis,the author analyzed the effect of LET on the single-event transient voltage of combinational logic circuits by performing device-circuit level hybrid simulation of basic gates,modeled the single event transient voltage by machine learning methods,and verified the validity of the model by comparing it with the single event transient voltage predicted by device-circuit level hybrid simulation.The accuracy of inverters,NOR-gates,and NAND gates was above 93%,96%,and 91%,respectively.3.Considering that the pulse widths of basic gates were different under the same LET,a combined logic vulnerability prediction model based on circuit level simulation was established on the basis of the second point.Firstly,the pulse widths of NAND gates,NOR gates and inverters under different LETs were calculated by using the single event transient voltage prediction model.Then,by adjusting the pulse width settings of the control part of the system,the corresponding pulse widths of the three basic gates were input respectively,and then the circuit error rates under different LETs was obtained.Finally,the circuit vulnerability of ISCAS'85 benchmark circuit under 40 nm process was analyzed.Experimental results showed that the prediction trend of this model was the same as that of other algorithms.