Thermal Chips Layout Method In MCM Based On A Hybrid Optimization Algorithm

The miniaturization and multi-functionality of electronic components has been widely concerned in recent years,particularly for multi-chip modules.Due to the ever-shrinking device size,the power consumption per unit area is getting larger and larger,making it more difficult for the system to dissipate heat.As a result,different device placement results in differences in temperature distribution.In view of this,this paper studies the thermal layout optimization method for multi-chip components,establishes the numerical relationship model between the junction temperature and the coordinates of each chip,and uses ANSYS Icepak software to simulate and analyze the temperature profile of the optimization results.Based on bPSO,an improvement measures proposed.In addition,in order to make up for deficiencies of PSO which easy to fall into the local convergence,this paper presents a hybrid optimization algorithm based on the global convergence of SA.The thermal layout design method proposed in this paper can not only provide a more uniform layout of the substrate coordinates,lower the junction temperature of the chip,but also effectively solve the problem of overlap and out of bounds.The main contents of this article are as follows:(1)Introduction of Chip layout background.The article first introduces the background and research status of chip thermal layout,the characteristics and development of multi-chip module technology.Then introduced the PSO and SA in different areas of improvement and application status.(2)Pretreatment of chip initial layout.Because the initial layout of PSO is random,the position of the PSO directly affects the quality of the final optimization results.Therefore,this paper proposes a staged random layout method at the beginning of the algorithm,that is,the substrate is divided into four parts,and then the chip in accordance with the size of the power distribution in turn.In addition,PSO uses the chip as a particle to optimize the calculation,ignoring the actual size of the chip,making the actual layout in the chip overlap and out of bounds,so this article also added the corresponding geometric constraints.(3)Research on the improvement of bPSO.The ultimate goal of this paper is to find the best chip thermal layout method to reduce the chip maximum temperature and maximum temperature difference.In order to achieve this goal,this paper successfully applies PSO to chip layout.However,the bPSOA has many disadvantages,so this article first compares several typical optimization schemes based on w,and then further optimizes it.In addition,the control factors such as Vmax of the chip moving updating equation and the iterative convergence condition are also improved correspondingly.(4)Proposed combination optimization algorithm.Easy to fall into the local extremum can be described as the weakness of PSO,in contrast,the global convergence ability of SA outshone.In view of the advantages of the two algorithms,the article combines the two algorithms into one,and presents a hybrid optimization algorithm.In the meantime,the calculation of the objective function is also carried out by using the response surface method.The optimal layout position of the chip in the natural convection environment is found through the junction temperature model.(5)Programming and application of software.Prepared combined with junction temperature improved PSOA and the combination of procedures.Program results include the chip’s position coordinates,the estimated junction temperature of each chip,and the recording of convergence conditions.In this study,thermal simulation software ANSYS Icepak was also used to model and the statistical analysis software SAS was used to fit the equations.The final layout results were verified by simulation.