| The development of related technologies such as the Internet of Things has promoted the widespread application of MEMS sensors including MEMS capacitive accelerometer in wearable devices,which has limited the size and power consumption of accelerometers during the design process.In addition,the feature sizes in the CMOS process and MEMS process for MEMS sensors manufacturing are reduced in order to comply with the trend of highly integrated MEMS sensors.These will cause the power supply voltage of the accelerometer to decrease and be susceptible to interference from parasitic capacitance,thereby reducing the dynamic range of the accelerometer.Therefore,in the process of designing a MEMS capacitive accelerometer,this paper has conducted in-depth research on its characteristics of low power consumption and wide input dynamic range,proposed corresponding implementation methods.In this paper,a sensitive unit model that can be used for the overall simulation of a circuit is established based on the physical structure characteristics of the capacitive sensitive unit.After studying the working mechanism of the capacitive accelerometer in detail,non-ideal factors such as thermal noise,parasitic capacitance,and electrostatic force pull-in effects are introduced on the basis of the ideal mechanical model,and the behavior model of the sensitive unit is established based on Verilog-A language.By analyzing the transient characteristics and frequency characteristics of the model,it is concluded that the established model can accurately describe the operating characteristics of the actual sensitive unit and can be simulated with the entire readout circuit.Secondly,by studying the working principle of different capacitive charge converters(CVCs)and analyzing their advantages and disadvantages,a fully differential split-loop structure composed of switched capacitor charge amplifiers is selected to realize the capacitance value reading.In order to reduce the parasitic capacitance’s deterioration of the input offset error and gain error in the readout circuit,the input common-mode feedback compensation structure and the oversampling successive approximation readout technology are introduced.After analyzing the shortcomings of the two circuit structures,a CVC using average noise reduction readout technology is proposed.This technology can make the input dynamic range of CVC reach 98 d B by reducing the noise in CVC,while reducing the overall power consumption of the readout circuit.In order to make the accelerometer output a stable digital signal,a one-bit quantized singleloop feedforward structured second-order Sigma-Delta modulator is designed in this paper.The modulator has high linearity and low power consumption.After studying the working principle and stability conditions of the modulator,a circuit implementation scheme is proposed.The effective number of modulators is 12 bits and the signal-to-noise ratio is 74 d B.Finally,based on the Dongbu Hi Tek 0.18μm BCD process,the design of the circuit system is simulated and verified in Spectre.The simulation results show that the readout circuit designed in this paper has an effective identification range of ± 10 g when the power supply voltage is 1.8V.With the decrease of the output sampling frequency,the increase in the output noise of CVC is suppressed to within 3d B,and the error between the actual value and the theoretical value is 1.08%,and the power consumption of the readout circuit is reduced by optimizing the overall circuit structure.The temperature coefficient of the bandgap reference module is 12.7ppm / ℃,and the rise time is less than 5μs,which meets the design requirements. |
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