Hardware Accelerated Implementation Of Hyperspectral Anomaly Detection Algorithm Based On Feature Extraction

The hyperspectral remote sensing imager can obtain three-dimensional hyperspectral images containing both spatial and spectral information.Through the spectral features of objects provided by hyperspectral image,we can complete the classification of objects,object detection and anomaly detection with high precision.Among them,the anomaly detection can detect the target with spectral difference from the surrounding environment without providing the prior information of the target spectrum in advance,and it can not rely on the complex preprocessing process such as atmospheric correction and radiation correction,so it is more suitable for the real-time processing application scene.It is very important to obtain the target information which is different from the background in time through the real-time processing of hyperspectral image anomaly detection.However,the continuous improvement of spatial resolution and spectral band number of hyperspectral imager brings dimension disaster of data and technical problems of processing,storage and transmission of massive data on satellite.The key problem is how to realize on-board realtime processing of hyperspectral image target detection on the premise of considering processing speed and resource consumption.For this reason,this paper takes RX algorithm as the research object and completes the hardware accelerated implementation of hyperspectral anomaly detection algorithm based on feature extraction on FPGA platform.The specific research work of this paper is as follows:First of all,the method based on deep learning is used to extract the features of hyperspectral images,and an efficient feature extraction circuit is implemented on FPGA.There are band noise and data redundancy in hyperspectral images,which affect the accuracy of pixel level outlier detection.In this paper,we use the deep belief network(DBN)to extract the depth features,and then design a high concurrent and high throughput feature extraction circuit,which can quickly adjust the number of layers and neurons in the layer,and has a strong universality.And then,in order to achieve the goal of real-time processing,the RX algorithm is improved,and the RX anomaly detection circuit is implemented on FPGA.RX algorithm needs to generate filter operator by statistical background covariance matrix,so there is a large-scale matrix inversion operation.In this paper,the Sherman Morrison fast inversion method is used to optimize the inversion process.The complex and increasing operation is optimized to a fixed scale iterative operation to complete the hardware implementation of Rx.Finally,the standardized and modularized hardware architecture of DBN-RX real-time processing is designed.The hardware circuit design method of FPGA based on HLS is used to improve the efficiency of hardware design and the iteration speed of architecture design.This paper focuses on the research of logic reuse and parallel pipeline design of algorithm modules to achieve the fastest data processing speed with the least cost of resources.Finally,it evaluates and analyzes the detection accuracy,resource consumption and detection performance.Experimental results show that the hardware architecture proposed in this paper achieves strict real-time processing speed,while maintaining the same high detection accuracy as the traditional algorithm.