FPGA Design Of Low-altitude Small UAV Detection Radar

With the widespread application of low-altitude,slow-speed,and small aircraft technology represented by UAV in civil scenes,places such as airports and open-air venues have increasingly urgent requirements for low-altitude security.LFMCW radar has the advantages of no blind area in short range detection,high range resolution of small target detection,simple structure and low cost,which is suitable for detection of small targets in low-altitude.FPGA can rely on its rich computing resources and high-speed interface to achieve powerful logical transaction control and digital signal processing,which can meet radar work control,signal processing requirements and real-time requirements.Therefore,in this thesis,the LFMCW radar system for low-altitude small UAV detection is designed and built.Based on FPGA hardware,the timing control and signal processing part of the radar system is designed,and the effectiveness of the radar system for UAV detection is verified by experiments.Firstly,based on the application scenario of low altitude small UAVs and the advantages of LFMCW radar system,the radar system framework is designed and established,and the functions and design points of each component of the system are described.This thesis analyzes the basic principle of LFMCW radar acquiring target parameter information through beat signal,designs and simulates the radar signal processing flow of pulse compression,digital beamforming,moving target detection,constant false alarm detection and dot condensation in MATLAB.In the meantime,realizes the angle measurement of target through beam scanning method.Secondly,FPGA is used to design and implement the work control and signal processing flow of the radar system.The framework of modular design is built and the clock domain of each module is divided.By analyzing the principle of RS-422 interface,the generation and sending of the frequency synthesis message are designed and implemented.SPI interface timing is designed to configure the working mode of clock chip AD9516 and ad chip ADS5263.Using the FFT,multiplier,FIFO,GTH and other IP core resources of FPGA,the algorithm flow of radar signal processing and the packet transmission of data are realized.The overall running time of the design is less than that of a PRT,the resources are used reasonably,the running timing meets the requirements,and the power consumption is low.Finally,the UAV test system is built with the radar components that have been debugged.In the actual UAV detection process,a clear track display is obtained,and the clutter points are optimized by various methods.The key parameters such as the gain of the receiving link of the radar system and the isolation of the system are tested,and a synchronization scheme of AD sampling results based on FPGA is designed,The noise power of the receiver is measured online by using AD sampling,all indexes meet the expected design standards.