Research And Design Of 76-81GHz Automotive Radar Phased-Array Receiver Front-End

With the rapid development of communication technology and the Internet of Things,intelligent driving came into being.Automotive radar,which is widely used in automobile detection and collision avoidance,has become a research hotspot in academia and industry.By beam scanning,phased array radar can achieve high measurement accuracy,high resolution and wide monitoring range.As a key module in radar communication system,the performance of receiver is very important.This paper designs an 8-channel 76-81GHz automotive radar phased array receiver front-end fabricated in CMOS 55-nm process.The main research results are as follows:1.By investigating the research results of phased array transceivers published in international first-class journals and conferences in recent years.The structure characteristics and technical indicators of the phased arrays investigated are analyzed in a list.The system structure of the 8-channel phased array receiver designed in this paper is defined.The working principle of the FMCW radar and the link budget of the FMCW radar are described.According to the link budget,the performances index of the 8-channel phased array receiver front-end are determined.2.A 64.5-88GHz broadband low noise amplifier fabricated in 55nm CMOS process is designed and tested.The low noise amplifier is composed of two stage common source circuit and one stage cascade circuit.The bias voltage is determined by the optimal noise method.To reduce noise,transformer-based dual-coupling G_m-boosted technique input balun is utilized,which is composed of three metal layers:one primary coil and two secondary coils.The two secondary coils are connected to the gate terminal and the source terminal separately.By cross-connecting the source output signal of the input balun,the voltages at the gate and source terminals become out-of-phase.Thus,the effective gate-source voltage swing is enhanced.The gain and noise performance of the first stage circuit is improved.Capacitive neutralization is utilized in the second stage to improve the stability of the circuit.The common-gate-shorting technique is used in the cascode stage to improve stability and gain.To achieve a wide bandwidth,the coupling coefficients of the transformer and the Q value of the coils are optimized and the transimpedance responses of the transformer interstage networks are jointly tuned.The chip area is 958*177μm².The power is 72.7m W。The test results shows that the input return loss S11<-10d B,the output return loss S22<-5.7d B,the gain S21>10d B,the stability factor K>7,and the noise figure NF<8d B.The input 1d B compression point（IP1d B）is-12.8 d Bm at 70 GHz and-12.2 d Bm at 80 GHz,respectively.FOM₁ and FOM₂ are 0.0155 and 0.0507,respectively,reaching the international mainstream standards.In order to reduce power consumption,a 76-81GHz low power amplifier is optimized and redesigned based on the tested broadband low noise amplifier.The amplifier is consisted of two stage common source circuit.The bias voltage is also determined by the optimal noise method and the source degeneration inductance is adopted for input matching.The post simulation results show that at tt corner,25℃,the input return loss S11 is lower than-6.5d B,the gain is 10-11.1d B,the noise figure is 6.4-d B over 76-81GHz with 19m W power.The input 1d B compression point（IP1d B）is-8.73d Bm at 78GHz.3.A 76-81GHz 5-bits passive phase shifter fabricated in 55nm CMOS process is designed.T-type network structure is chosen for the circuit.The transmission line and inductance are all self-modeled devices.Now the test is in preparation.The post simulation results show that at tt corner,25℃,the average loss is 14.1d B to 15.6d B,the RMS gain error is<0.58d B,the RMS phase error is<7.1°.Since the RMS phase error at 76 GHz is 7.1°,which is higher than 5.6°,it is not suitable for phased array design requirements.Thus,a 76-81GHz 5-bits hybrid phase shifter is optimized and designed,in which the 180°bit adopts active structure,and the remaining bits adopt passive structure.The post simulation results show that at tt corner,25℃,the average gain is2.7d B to 4.1d B,the RMS gain error is<0.44d B,the RMS phase error is<5°with69.5m W power consumption.4.Fabricated in 55nm CMOS process,the single element chip and 8 channel millimeter-wave phased array receiver front-end chip are designed.The post simulation results of the single element show that at tt corner,25℃,the average gain is 13.1d B to15.5d B,the RMS gain error is<0.43d B,the RMS phase error is<5.4°,the input 1d B compression point（IP1d B）is>-15.5d Bm with 88.5m W power consumption.The post simulation results of single channel of the 8 channel phased array show that at tt corner,25℃,the average gain is>10.1d B,the RMS gain error is<0.5d B,the RMS phase error is<4.7°,the input 1d B compression point（IP1d B）is-15.9d Bm to-15.2d Bm,the isolation of different channel is>30d B.The power consumption of 8 channel phased array is 725.5m W。The Peak-to-Null ratio is larger than 20d B,the Peak-to-Peak ratio is larger than 9d B and the Beamwidth_{-3d B} of 5.8°can be obtained for different azimuth angles.When the azimuth angle is 2.9°,the pattern results of 77GHz,78GHz,79GHz and 80GHz are basically the same.