Research On Power Management System For NB-IoT

NB-IoT(Narrowband Internet of Things)has been widely used due to its low power consumption and wide coverage.By integrating the power management IC and power discrete devices on one chip,one can reduce the power consumption of the NB-IoT system,shrink area,save cost,and increase battery life.A highly integrated power management system chip is a new challenge for future Io T systems.Our power management system chip design is based on UMC55 nm technology,and the main work is as follows:1.This system utilizes distributed power transmission topology.DC-DC is the first stage,with high power,high conversion efficiency,and large current capability.Multiple LDOs are the second level,providing multiple voltage domains for different cores in the NB-IoT RF front-end transceiver system.LDOs can work together to achieve a trade-off balance among improved response speed,low ripple,and power consumption.2.A buck DC-DC is designed with synchronous rectification technology and PWM control mode.For an input voltage range of 2-5V,the output voltage is 2V,the maximum load capacity 100 m A,the conversion efficiency higher than 85%,the startup time 860 us,and the output ripple 22 m V.3.There are three on-chip LDOs with low output ripple,fast response,and low power consumption.Both the low output ripple LDO and the fast response LDO are based on the double-loop structure of the flip voltage follower.The low output ripple LDO ensures that the loop bandwidth is wide enough to enhance the drive capability of the loop and reduce the output ripple.For an output voltage of 1.8V,the static power consumption is 65 u A,and the load current jumps from 0m A to 30 m A within0.5us.The overshoot/undershoot voltage is 27 m V/39 m V.The fast response LDO uses NMOS as the power device to ensure sufficient loop drive capability.It increases the loop bandwidth,and achieves fast response.The output voltage is 1.2V,while the static power consumption is 58 u A,the load current jumps from 0m A to 20 m A within100 ns.The setup time is 159ns/120 ns.The low-power LDO reduces power consumption through a single-stage OTA with a 60 d B gain achieved by a sub-threshold current reference circuit with a 250 n A current consumption.The output voltage is 1.8V and the static power consumption is 1.5u A.A buffer stage circuit is added to enhance the circuit drive capability and improve Transient characteristics.Finally,the chip layout was completed in accordance with the corresponding process requirements and rules.