Research On An Integrable Lateral High Voltage Device For AC-DC Conversion

LDMOS is widely used in the field of power integration because of its compatibility with BCD and CMOS processes,such as AC-DC circuits,switching power supply circuits,LDO circuits,drive circuits,and so on.As a power switching device,LDMOS should not only have a higher off-state breakdown voltage,but also should have a smaller power loss in the on-state.Therefore,the breakdown voltage and specific on-resistance of LDMOS are the main indicators to measure its performance.However,the contradiction between the two determines that the breakdown voltage that LDMOS can withstand and its specific on-resistance cannot be compatible.It means that LDMOS will produce greater power loss in applications that require high withstand voltage.Therefore,there is a contradiction between BV and Ron,sp.LDMOS cannot simply increase the breakdown voltage by increasing the length of the drift region.It also requires necessary technical means to increase the drift region while minimizing the device’s Specific on-resistance.This paper studies a quadruple RESURF LDMOS with PNP layer.On the basis of the traditional Single RESURF LDMOS,P-buried layer,N-top layer and P-top layer are injected sequentially.The P-top layer is injected below the field oxide layer,the N-top layer is injected below the P-top layer,and the P-buried layer is injected below the N-top layer.On the one hand,the structure has four PN junctions in the longitudinal direction of the device.When in the off state,the four PN junctions are in the reverse bias state,and the two heavily doped P-type layers and the P-substrate assist depletion N-type layer and N-well reduce the effective concentration of the N-type region when the device is at withstand voltage,so that the drift region can withstand more voltage drop,and the withstand voltage of the device can be improved.If a part of the withstand voltage is sacrificed and the withstand voltage of the device remains unchanged,under the auxiliary depletion effect of the P-type region,the doping concentration of N-type impurities can be increased and the on-resistance of the drift region can be reduced;on the other hand,The existence of the top layer keeps the conductive path away from the surface of the device and optimizes the surface electric field distribution of the device.To a certain extent,it reduces the injection of hot carriers into the field oxide layer under the action of an electric field,which causes the specific on-resistance to increase and the breakdown voltage to change.With a small probability,the hot carrier reliability of the device is improved.Then,this article derives the silicon limit model of the studied new RESURF LDMOS,and obtains the silicon limit relationship of R_on,sp=5.93×10^-6×47.90×BV^11/6.In addition,through the results of device simulation,the deduced silicon limit model was fitted.In order to simulate the actual manufacturing process,through process simulation of the device,the withstand voltage and specific on-resistance that can better fit the model are obtained,where BV=766V,R_on,sp=66.4 mΩ·cm².In order to ensure that the device reaches a relatively stable charge balance state and a RESURF condition where the drift region is fully depleted under the reverse withstand voltage condition when the device is in the off state,the injection dose and energy of each step have been repeatedly adjusted.Through the optimization of the bird’s beak area,the optimization reduces the peak value of the electric field in the bird’s beak area,which not only improves the withstand voltage of the device to a certain extent,but also effectively improves the hot-carrying effect of the bird’s beak area of the device.Compared with Triple RESURF LDMOS devices with NPN layer based on the same high-voltage integrated process platform and similar breakdown voltage,the quadruple RESURF LDMOS with PNP layer studied in this paper has a lower specific on-resistance.Through simulation and comparison of the surface electric field distribution,the generation rate of electron-hole pairs and the hot carrier injection efficiency of the two,it is reasonable to explain the reason why the hot carrier degradation of the new device studied in this paper can be improved.