Research And Design Of High Efficiency Hybrid Step-down DC-DC Converter

In the power management IC used in battery-powered portable electronic equipment,the proportion of inductive step-down DC-DC converter is significantly higher than that of other types of converters.With the continuous upgrading of personal consumption levels,the number and performance of the required portable electronic devices have increased significantly.Therefore,this will require the power management chip to have high efficiency,and at the same time,it must also meet the conditions of small size of peripheral devices and low heat generation.This will pose a great challenge to the design of conventional inductive step-down DC-DC converter chips.The conventional inductive step-down DC-DC converters require off-chip inductance with smaller parasitic resistance,thereby reducing losses,reducing heat generation,and improving overall chip efficiency.However,since the parasitic resistance on the inductor is inversely proportional to its volume,the increase in efficiency will result in a significant increase in volume,which violates the requirement of small peripheral device size.To alleviate these problems,this thesis proposes a hybrid step-down DC-DC converter structure,which transfers energy through dual paths of inductors and capacitors,so that the average current of the inductor is greatly reduced.The loss of the resistance can well meet the requirements of high efficiency,low heat generation,and small size of peripheral devices.In this thesis,the working principle of traditional DC-DC converter is briefly introduced,and the state space averaging method for modeling and analysis is described in detail,as well as the mode control principle and the basic theory of loop compensation.Then the operating principle of the topology structure of the converter proposed in this thesis is emphatically expounded,and the modeling analysis is carried out.Then the specific design of each part of the circuit module is given,including power level circuit,drive circuit,PWM circuit,compensator circuit and other important sub-modules.Finally,the 0.18μm CMOS process is used to design the circuit,and the simulation results of each circuit block and the whole circuit of the system on Cadence Spectre platform are given.The hybrid step-down DC-DC converter structure proposed in this thesis can output a voltage range of 1.36-2.55 V and a load current range of 0.1-2A when the input voltage is3.4V,and the parasitic resistance of the simulated inductor is set to 50mΩ-250mΩ.Simulation results show that the peak efficiency can be maintained above 90% over the entire output voltage range.Under different parasitic resistance of the inductor,the peak efficiency can reach 95.77%,and even at 250mΩ,the peak efficiency is about 93.78%.Therefore,the design of this thesis can well meet the preset index requirements.