Research And Design Of DLL-based High-precision And High-stability Delay Line DPWM

With the rapid development of the semiconductor,the performance of the digital switching converter is improved quickly.Compared to the traditional analog switching converter,the digital switiching converter realizes multi-phase control,non-linear control,fuzzy control,load share,failure prediction and so on.Meanwhile,it has the advantages that the intergration level is high and the hardware need not to be replaced when the performance indicators are changed.Since the ADC module has been realized the high resolution,to avoid the limit cycling phenomen ouccring,the digital pulse width modulation(DPWM)module with the high precision and high stability becomes the research hotpot.With the increasing resolution,the duty cycle in DPWM is affected by the variation of external clock frequency or temperature,and the time error becomes larger and larger,even reaches a few nanoseconds.The increment phenomena of the duty cycle will affect the regulation performance of the converter and the output of DPWM.In view of the abovementioned problem,a delay-line DPWM architecture with a critical path compensation module and a delay-adjustable unit based on delay-locked loop(DLL)is proposed in this paper.To reduce the effect of the output duty cycle caused by the changing external factors,the delayadjustable unit realized by a multiplexer and some delay paths with different delay times is used,and its delay time is automactically adjusted by the delay control module.Furthermore,to reduce the effect of the ncrement phenomena of the duty cycle,the critical path compensation module is used,and the unexpected transmission delay on the critical path is compensated.In this paper,a 10-bit delay-line DPWM with 781 k Hz switching frequency is designed.The simulation and actual experiment are achieved on Vivado and A-7(xc7a100tfgg484)Xilinx FPGA,respectively.The time error generated by the variation of input frequency or temperature is obtained by the control variable method,and the time error of the architecture is around 500 ps.In addition,the output duty cycle range is approximately from 1.63% to 98.44%.The experimental results shows that the stability of the proposed DPWM architecture is better than others,and it has wide application prospect.