Study On The Yield Improvement Of The Assembly Of Flip Chip Components

Nowadays,the mobile communication products trend to a short thin direction,the process is more complicated than before,production yield improvement is more difficult,especially when the IC(integrated circuit)package evolve from BGA to Flip Chip,usually encounter some yield problems.In this paper,the IC development of the form,Chip Flip package,demands and applications are introduced.This paper also focuses on the research of the assembly process,failure analysis,yield and problems encountered with the practical application.Through the DOE verification methods:(1)Flip Chip material cosmetic inspection,especially the inspection of solder bump.Sampling 32 pieces from each batch to eliminate the incoming defects;(2)Change the PCB PAD design for Flip Chip area.Change the pad area from non-solder mask design(NSMD)to solder mask design(SMD)when the pad pitch is less than 0.45mm,and restrict the Z height from 6?m to 18?m,limit W to 1.1?1.2 width of UBM at the Flip Chip top side in order to reduce 13.5%defect rate for insufficient-filled glue;(3)Change PCB PAD surface treatment.Surface treatment changes from NPR4 to the stronger antioxidant NPR8 for black pad problems.It can reduce 3%non-wedding issue;(4)Reduced the stress that is from the CTE difference between the substrate and the Flip Chip.It shows the loss rate can be reduced by 1.81%when pre-baking at 125?in a nitrogen(N₂)flow of 80LPM(Liter Per Minute)for 4hours to eliminate the moisture.When those improvement methods are introduced together,the defect rate can be reduced to about 0.145%,and the final yield can be improved by 18.165%.In order to avoid similar problems recurring in new cases,these methods have been introduced to the CTF(Critical to Function)check list and integrated as a project tree,then mapped to the DFX library and design library and eventually to achieve the continuous improvement with less detours in new developing cases.