Design And Research Of Single-slope ADC Applied To Image Sensor

In the readout circuit of the CMOS image sensor,the column-level ADC has the feature that each column of pixels in the pixel array shares an analog-to-digital converter.Compared with the pixel-level structure,it does not use an ADC for each pixel,which greatly reduces the number of ADC,saves the area and power consumption of the pixels,making the fill factor of the pixels higher than the chip-level structure,that is,the use of one ADC for the entire pixel array reduces the ADC’s performance requirements and makes the design easier.In addition,the multi-channel parallel operation of the column-level ADC is more suitable for large pixel arrays,and the area and power consumption are relatively small.Based on this background,this article has designed a column-level single-slope ADC with high accuracy,low power consumption,and easy adjustment for image sensor readout circuits.Due to its simple column-level structure and the characteristics of shared modules,it has better consistent matching between columns and reduce fixed pattern noise(FPN)between stages.The principle of single-slope ADC generating high-precision,high-linearity ramp signals and the comparison of various structures used were studied,an adaptive adjustment mechanism was introduced.And a feedback loop was added to the switched capacitor integration circuit to realize the adaptive adjustment of the ramp output signal.At the same time of the linearity of the ramp signal,the slope has a higher accuracy.The resolution can also be adjusted by adjusting the ratio of the step capacitor,and the number of ADC bits can be expanded to meet the different test requirements of the ADC.The op amp used a two-stage structure with high GBW,and common-mode input range,and was connected to unity gain as a ramp output buffer,which made the ramp signal have better driving ability and reduces the impact of the subsequent dynamic comparator on the ramp signal due to clock transitions.For the input offset voltage of the comparator,a three-stage preamplifier cascade structure was designed,and the auto-zero technology for redistributing the charge was used to greatly reduce the input offset.Adding a dynamic comparator increases the speed of the comparator.In view of the susceptibility of analog signals to digital signals,a digital-to-analog power supply was used to ensure the integrity and accuracy of the analog signals.The counter used a 10-level TFF cascade structure to form an asynchronous counter with a small delay.The code density analysis method was used to collect the ADC output for nonlinear testing,and the fast Fourier transform method(FFT)was used to test the dynamic performance of the ADC,and the data was processed with Matlab.The design is based on the CMOS 0.13μm process.The overall circuit design and simulation optimization and layout design of the 10-bit single-slope ADC were performed.The core area of the chip is 600?460μm~2,and the analog and digital parts are powered by 3.3 V.While achieving high-precision conversion,the working speed of the ADC was increased to 35KHz;the non-linear error DNL of the ADC measured by code density analysis was+0.53/-0.16LSB,and the INL was+0.38/-0.38 LSB;ADC input sinusoidal signal,measured SNDR is60.8d B and ENOB is 9.8 bits under TT process angle;the slope generator and counter module of single-slope ADC are shared at the column level,and the register adopts pulse control to reduce the working time,power consumption is less than 100μW.