Physical Design Of FT-DMx High-performance Anti-irradiation DSP Core

As China's aerospace technology enters a critical moment of rapid development,the demand for self-designed high-performance radiation-resistant integrated circuits is becoming more urgent.Physical design is the bridge between integrated circuit logic design and layout implementation.As the chip scale increases and the process size shrinks,the chip voltage drop,electromigration,and signal crosstalk problems become more and more serious,and the chip's radiation resistance requirements also give physical Design brings huge challenges.Therefore,under the research of advanced technology,the physical design of anti-radiation chip is of great significance.The FT-DMx anti-irradiation multi-core microprocessor is a multi-core DSP SOC chip for video image processing.This article takes its high-performance DSP core as the design object and adopts a 40 nm anti-irradiation process to complete the layout design from Netlist to Layout.,To achieve the goal of 400 MHz,and detailed analysis and optimization of the key steps in the physical design process.Firstly,according to the semi-customized design method of anti-irradiation chip,the unit anti-irradiation hardening technology is introduced,and the extra cost of the anti-irradiation cell library hardening design in area,timing and power consumption is analyzed.In the layout design stage,by analyzing the data path and logic synthesis characteristics of the DSP core,several layout regularization schemes were proposed to optimize timing and reduce congestion.Afterwards,for the purpose of optimizing electromigration,voltage drop and congestion,the design and verification of the power network were carried out.In the clock tree synthesis phase,the automatic clock tree synthesis method is first used to analyze and design the selection of clock drive units and the clock tree synthesis constraints in detail,and propose a solution to the problems of clock latency,Skew,and excessive number of clock stages An automatic clock synthesis method based on different regions optimizes and reconstructs the multi-level gating of the design,reducing the clock latency by 33.4% and Skew by 23.2%.Aiming at the problem that SET has a serious impact on the reset network,this paper proposes two anti-irradiation hardening methods in combination with the anti-irradiation unit library,and strengthens the reset network by writing scripts.In the wiring stage,the antenna effect is eliminated by the wiring layer jumper and the reverse bias diode insertion,and the crosstalk of the design is optimized.Finally,a static timing analysis is performedon the design,and the timing violation of the design is fixed.Based on the 40 nm anti-irradiation unit process,this paper completed the physical design of the FT-DMx DSP core,with a module size of 710,000 Instances.It meets the design requirements through timing repair,design rule check,and schematic and layout consistency check.Finally,the main frequency of the chip is 400 MHz,the area is10025341.2?m2,the power consumption is 1512.3m W,and the voltage drop of the chip is controlled within 5%.The physical design of the chip involved in this article has a certain specificity,and the module size is large,the process is advanced,and the clock structure is complex.Therefore,the relevant work of this article will have reference significance to the physical design of the irradiated chip.First,the automatic clock synthesis method proposed in this paper has a good optimization for the design of complex gating logic,large module area,large number of units,and complex clock structure in terms of reducing clock latency,Skew,and optimized timing.effect.In addition,the comprehensive process of reset network and the method of redefining the root node used in this article will have a good reference and reference for reset network design or other similar network design using the specified unit.