Design Of Digital Audio Equalizer In The Chip Of Intelligent Speaker

As an important hardware in the audio processor,the equalizer plays a vital role in the beautification of the sound signal.With the rapid development of digital audio technology in the twentieth century,the performance of the original analog audio equipment has been greatly improved,the equalizer has been transformed into digital equipment gradually,and the processing of sound signals has been transformed into digital signal processing with each passing day.The research purpose of this paper is to design a digital audio equalizer based on ASIC,so as to improve the resource utilization of the hardware.The main work is to finish HDL modeling,functional verification and synthesis in the ASIC front-end design.The design process adopts a circuit synthesis method based on HDL,while the function verification is performed according to the UVM,and finally a circuit netlist without any function error is obtained.This article focused on the HDL modeling.In order to meet the accuracy requirements of the end product for equalizer,a high order filtering system is needed inside the design module.The series-connected structure of IIR is stable in performance,but it needs a large number of computing units to support its algorithm,which will definitely cause a large waste of hardware resources.Therefore,after considering the influence of circuit structure on synthesis area and power consumption,many module are reused in the hardware designing,which is also the innovation of this article.Throughout the module,there are only one multiplier,one second-order IIR unit,and one single-port SRAM.The function of high order filter is achieved through the repeated use of the IIR unit,and the calculate operation of this IIR unit is also performed by reusing the multiplier.This SRAM is used to store the tap coefficients required for each calculation.Meanwhile,there is a special control circuit to command each input signals and tap coefficient storage,so as to guarantee the correctness of each filtering operation.In addition,registers in this module support APB bus access,and the registers could be configured externally in actual use to control the number of filtering times,this makes the equalization accuracy controllable and increases the flexibility of the end product.The function verification of the design module is performed in accordance with the UVM.This article establish its own verification platform for the design,finish each component with System Verilog,and create 3 test cases.For each test item,after analyzing the simulation waveform and viewing the log file,find that the function of design module is correct.Code coverage is subsequently collected and the result shows 98.62%,which meet the project requirements.Thus it is judged that the design module has realized the expected function,and the verification work is completed.This article use DC to finish synthesis for the design module under the TSMC12nm library.By reviewing the comprehensive report,there are no timing violations on the critical path.At the same time,the area data and power consumption data of the Netlist are collected,which are 29961.449?m~2 and 1.17m W respectively.Thus it is found that the design requirements are met and the achievement of design scheme is highlighted.