Research On Verification Of Asymmetric Algorithm IP Core Based On UVM

Intelligent security systems such as smart cards and smart access controller,which are widely used in important fields such as public transportation and identity recognition.In these systems encryption and decryption of the data input/output,data transfer and data processing are very important.However,the integration of the encryption and decryption algorithm module will lead to the increasing scale of integrated circuit(IC).The usage of intellectual property(IP)cores are large.At present,the complexing IC function verification has become a bottleneck of IC design flow.Efficient verification will guarantee the correction of function design and improve design productivity.In this work universal verification methodology(UVM)is used to verify the functional of the asymmetric algorithm module in the universal encryption and decryption algorithm IP core CE(Crypto Engine).The research works and results are as follows: 1.The principles,platform framework,communication methods,operation methods and various mechanisms of CE module were thoroughly analyzed under the UVM verification methodology.Combined with the description of the function and structure of the CE module,the description of the interface and registers,the basic operation flow,the detailed description of the task descriptor,and the principle and implementation of the asymmetric algorithm,the functional test points of the CE module were fully extracted.2.The verification plan of the CE module was formulated.The UVM verification platform was constructed.The entire verification environment was divided into three parts according to the external port of the module: AHB(Advanced High Performance Bus),MBUS(a high-performance bus protocol defined by Allwinner Technology)and CE sub-environment.The AHB sub-environment is used to simulate the CPU controller of the CE module.The MBUS sub-environment is used to read encryption and decryption data and descriptors of the algorithm.The CE sub-environment is mainly used as a driver of other ports,the generator of task descriptor queues,the construction of monitors,reference models,and scoreboards.Then,add excitation generators as the driver for the entire CE module.Further more,the three fully created child environments and other verification components were instantiated into the TOP＿ENV parent environment,finally a complete and highly reusable UVM verification platform was established.3.Highly efficient verification result was obtained based on the UVM verification platform.Above,a verification catalog of CE modules was established to standardize the verification environment.Scripts were used to implement verification automation,and the verification efficiency was significantly increased more than 20 times.The functional test points of the CE module are verified by using coverage as a criterion to judge the quality of verification work.The code coverage reaches 97.40%,which indicating that the code had been executed meet the requirement.The function coverage reaches 100%,indicating that all the functions of the module are designed as expected.Assertion coverage reaches 100%,indicating that all the timing relationship between the specified signals met the requirements.Eventually the goal of complete verification was achieved.