Design And Implementation Of Automatic Visualization In Logic Verification

With the rapid development of the IC(Integrated Circuit)industry in recent years,the difficulty and complexity of chip circuit design are increasing day by day,and the most important link that restricts the continued rapid development of the integrated circuit industry is chip verification.The current chip verification workload in commercial chip design is unimaginable.Efficient chip verification can allow companies to reduce tape loss,speed up chip mass production cycles,and improve design quality.The automatic visualization technology implemented in logic verification is a mainstream direction for the development of chip verification efficiency in the future,and it is the direction that this article focuses on implementation and exploration.This article also proposes a specific implementation scheme for automatic visualization verification.The research goal of this paper is to use automatic visualization technology to improve the verification efficiency.The specific implementation method of the research goal is to design an automatic visualization data processing platform to reduce the workload of the data processing link in the chip logic verification and realize the data processing link in the logic verification Efficiency,so as to achieve the design purpose of improving verification efficiency.The automatic visual data processing platform designed in this paper is composed of automatic data collection module and data visualization presentation module.The data automatic collection module mainly relies on Python language and UVM methodology,and integrated EDA verification platform.The data visualization presentation module mainly relies on Python language,Web framework,Linux system,and database technology.The automatic visual data processing platform designed in this paper integrates software data processing and hardware verification technology,and this article sets up many humanized functional components in combination with its own internship experience to improve the user’s experience and facilitate the verification staff to complete daily data processing work.In order to realize the platform designed by this article,the first step is to set the parameters of the currently used UVM platform information report module,and use the standardized data output mode provided by the UVM methodology to obtain the verification data processing objects required by this design.The next step is to use this article.The designed automatic visual data processing platform performs a series of technical processing on the standardized output data obtained from the UVM platform according to the requirements in actual verification work,and then uses the visual web terminal to realize the data presentation and management.Thus,a complete set of automatic visual verification data processing flow designed in this paper can be completed in different logic verification processes.The verification data processing platform designed in this paper can be directly put into actual verification work to realize the automatic management and visual presentation of verification data.Effectively reduce the workload of verification engineers and the difference in data processing results caused by data processing,and realize standardized data management.Effectively improve the efficiency of data processing in logic verification.The traditional visual automated verification method is mainly to design an automated code generator that automatically generates test cases and verifies platform code.Compared with traditional methods,the visual automated data processing platform designed to process verification data in this paper has the advantages of high practicability,wide application range,good reliability and strong linkage.The design direction of this article also opens up a new way to achieve automatic visual verification,which is to effectively integrate,innovate and expand the existing practical technology based on the actual verification work requirements.