| With the rapid development of the microelectronics industry,electronic products are constantly moving towards miniaturization,high integration,multifunction,and low cost.The traditional way is to reduce the feature size of the device,thereby reducing power consumption and increasing integration,and the three-dimensional integration technology solves the problem of traditional microelectronics technology gradually approaching the physical limit by stacking chips in the vertical direction.The technology has been extensively studied.Multi-layer chip bonding is one of the keys to three-dimensional integration technology.Different layers of silicon wafers are bonded to achieve structural and electrical interconnections.This paper focuses on the multi-layer chip bonding process in three-dimensional integration technology and the reliability of the bonding interface,and proposes the use of electroplating to achieve two-layer through-silicon via bonding scheme.First,the electroplating bonding process is studied,including the use of wet etching of through silicon vias,the use of thermal oxidation to oxidize the insulating layer of through silicon vias,and the use of magnetron sputtering to achieve the deposition of via barriers,And the use of simulation to study the electroplating bonding process.Secondly,the thermal reliability issues,electrical reliability issues,and thermoelectric coupling reliability issues of three-dimensional integrated coppercopper thermal diffusion bonding process,copper-tin eutectic bonding process,and electroplating bonding process were simulated.Finally,the electrical properties of the three bonding processes are simulated,as well as the thermal fatigue problems in the high and low temperature impact experiments.Based on the experiment and software simulation,the bonding of the multilayer chip is completed.Through multiphysics analysis,the influence of different bonding processes on the reliability of bonding interface was studied. |
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