Design Of 12-bit 500KSPS Successive Approximation Register ADC Based On 14nm FINFET Process

With the development of computer,wireless communication and other technical fields,the digital processing of information has been widely used.Now the entire human society has entered the digital age,and various digital electronic products have emerged.In the real environment,the information that people touch,such as sound and light,is mostly analog.Therefore,the design of an analog-to-digital converter for converting analog signals into digital signals has become one of the key technologies of digital information processing systems.Among them,Successive Approximation Register(SAR)ADCs stand out among many ADC types due to their advantages of low power consumption,simple structure,and small area.Based on a certain SoC system application,this paper designs a 12-bit fully differential SAR ADC.The main contents are as follows:1.Briefly describe the basic theory of ADC,including working principles,performance parameters,structural features,advantages and disadvantages of different types of ADCs,etc.2.Explain the design of SAR ADC peripheral circuit,including high and low voltage level conversion circuit and reference source circuit.Because in the SoC system,the digital circuit and ADC circuit use 0.8V and 1.8V power supply respectively,therefore,the high and low voltage level conversion circuit is used to realize the conversion between 0.8V and 1.8V level to meet the connection between the digital circuit and the ADC demand;At the same time,the built-in bandgap reference provides a stable positive and negative reference level and common mode level for the ADC core circuit.In the design of the bandgap reference source core circuit,the voltage divider resistor adopts the Engineering Change Order(ECO)solution,it is convenient to locate the problem and modify quickly later.3.It focuses on the design of SAR ADC core circuit,In the capacitor array design,a segmented capacitor structure is adopted.The bridging capacitor between the two capacitors replaces the fractional capacitor with a unit capacitor,and the redundancy is shifted to the last one of the high positions to achieve an increase in linearity without affecting the linearity.The matching of the entire capacitor array is improved.At the same time,the capacitor array is designed into a fully differential structure and combined with backplane sampling technology to reduce the non-ideal effects of charge injection and clock feedthrough.The Bootstrap switch structure is used in the design of the sampling switch to realize that the switch resistance is not related to the sampling signal,and further improve the linearity of the circuit.In the comparator design,a pre-amplified and latched structure is used to meet the requirements of high resolution and high comparison speed,and the output offset storage technology is combined to reduce the impact of the comparator offset voltage on the entire circuit.4.The precautions and design specifications for layout design are introduced,and the overall layout design and circuit simulation of the SAR ADC have been completed.This paper is based on the SMIC 14 nm FINFET process for circuit design,with a layout area of 186μm×136μm.The post-simulation experiment results show that under 1.8V supply voltage,the sampling rate is 500 kHz,the SNR is 64.43 dB,the SNDR is 63.72 dB,the THD is-72.12 dB,the SFDR is 72.26 dB,the ENOB is10.29 bit,and the power consumption is 3.85 mW.