Design And Verification Of CMOS Frequency Synthesizer Based On TSMC 0.18μm

Since 1980s,with the progress of wireless communication,the demand for frequency synthesis has become increasingly urgent.In recent years,with the continuous evolution of mobile communication from 2G（GSM）,3G（CDMA）,4G（LTE）to 5G（NR）,the GHz level frequency generator is needed to provide the local oscillator frequency.Therefore,the demand for frequency synthesizer chips which can provide high frequency stable signals is increasingly urgent.With the development of integrated circuit technology,frequency synthesizer chip has been developing towards miniaturization,low power consumption,high frequency and low cost.Charge pump phase-locked loop is widely used in the design of frequency synthesizer because of its advantages of small phase error and large capture range.Firstly,this paper introduces the theoretical basis of PLL system,analyzes the working principle of each component of PLL and formulates it.Then the paper puts forward the basic concepts and generation mechanism of jitter and phase noise,introduces several non-ideal effects,and gives methods that can effectively solve non-ideal effects such as the dead zone of phase detector and current mismatch of charge pump.In this paper,the phase-locked loop system is modeled and analyzed theoretically.The source of the phase noise is analyzed through the transfer function.This paper also introduces the Leeson model to do the analysis of phase noise of VCO.Subsequently,each module of the phase-locked loop is designed by Verilog-A programming language.After defining the design parameters of PLL(reference frequency is 4MHz,output frequency range is from 4.1GHz to 4.4GHz,regulation sensitivity K_VCOis 100MHz/Hz),the parameters such as VCO free oscillation frequency,K_VCOand frequency division coefficient can be flexibly changed by Verilog-A language.With the help of modeling and simulation results,the influence of various parameters on the locking time and stability of the loop can be easily observed,so as to provide appropriate parameters for subsequent schematic design.This paper also proposes a fast lock-in phase-locked loop structure,which can increase the locking speed by increasing the charge pump reference current I_cpor the equivalent resistance R of the loop filter.Then we design the circuit schematic diagram.After the design and verification of the phase detector,charge pump,voltage controlled oscillator and divider modules,the whole circuit is simulated.Subsequently,layout design and post-simulation verification are carried out.The simulation results show that the PLL is locked normally after 20μs.Finally,we test the phase noise performance of the bonded chip.The result shows that the phase noise is approximately-81.83d Bc/Hz@1MHz and the power is only 0.31d Bm when the center frequency of the output signal is 4.3GHz.The system has the great phase noise performance.