Design And Optimization Of Novel Gate-all-around MOSFET Device

With the rapid growth of the integrated circuit industry,the requirements for the performance and size of semiconductor devices are higher and higher.The feature size of MOSFET will scale to 5nm by 2021,and gate-all-around MOSFET is considered the candidate structure due to its excellent gate control capability.In order to maintain excellent device characteristics at low feature size,the design and optimization of novel gate-all-around MOSFET devices with high performance and low power has become the research hotspot in the field of semiconductor.This paper is oriented to the urgent need of integrated circuits for novel gate-all-around MOSFET with high-performance and low-power.Focusing on the technical problems such as how to improve gate control capability and reduce the power consumption at low feature size,the embedded gate structure,GaN channel and the embedded insulator structure are proposed.Based on the above structures,a variety of novel gate-all-around MOSFET devices are designed and optimized,which improves gate control capability,reduces the power consumption of the devices,and solves the problems faced by gate-all-around MOSFET due to feature size scaling.The main research results and innovations of this paper are as follows:Firstly,for the problem that the gate control capability and subthreshold characteristics of the gate-all-around MOSFET is reduced due to the scaling of feature size,this paper researched the factors that affect the gate control capability of MOSFET,proposed the embedded gate-all-around MOSFET based on the embedded gate structure.The contact area between the gate and the channel is increased and the gate control capability is improved.The simulation results show that the subthreshold slope of the embedded gate-all-around MOSFET is as low as 65.5mV/dec,which is less affected by channel thickness,and the subthreshold slope decrease is about 1/2 of that of double gate-all-around MOSFET.Secondly,for the problem of increased parasitic capacitance and reduced switching speed of the gate-all-around MOSFET due to the scaling of feature size,the GaN embedded gate-all-around MOSFET based on the embedded gate structure and the GaN channel and its manufacturing plan are designed.The parasitic capacitance of the device is reduced,the switching speed is improved,and the subthreshold characteristics are less affected by the temperature changes.The simulation results show that the GaN embedded gate-all-around MOSFET exhibits excellent subthreshold characteristics with subthreshold slope as low as 63.8mV/dec and switching current ratio as high as 3.87×106.Compared with GaN nanowire gate-all-around MOSFET and double gate-all-around MOSFET,this structure has better switching speed and power consumption.Finally,for the problem that the leakage current and power consumption of the gate-all-around MOSFET is increased due to the scaling of feature size,this paper designed the embedded insulator gate-all-around MOSFET based on the embedded gate structure and the embedded insulator and its manufacturing plan.The leakage current and power consumption of the device are reduced.The simulation results show that the off-state current of the embedded insulator gate-all-around MOSFET is as low as 4.5×10-12A/μm,which is about 10 times lower than that of the double gate-all-around MOSFET and greatly reduces the power consumption of the device.