Suppression Technology For Timing Variations Due To Random Dopant Fluctuation In Nanometer CMOS Inverters

In the past few decades,complementary metal oxide semiconductor（CMOS）technology has dominated the mainstream semiconductor integrated circuit（IC）technology.Controlling short-channel effects,increasing operating speed,reducing power density and improving manufacturing yield have become key challenges for nanoscale ICs.On the one hand,circuit speed/frequency and dynamic power consumption are greatly affected by timing characteristics,and dynamic response time has become the main concern of IC design;on the other hand,intrinsic process changes during the manufacturing process also play an important role in IC.Especially when the technology node enters the nano-scale,the channel ion position and quantity fluctuation caused by doping and implantation（RDF）greatly changes the electrical characteristics of the semiconductor device in the sub-threshold region.Therefore,the timing fluctuations caused by RDF pose a huge challenge to IC design,manufacturing performance and yield.This thesis uses HSPICE and Sentaurus TCAD tools to carry out numerical simulation and statistical analysis of the electrical characteristics of nano-CMOS devices,and explores the influence of random doping on the timing of CMOS inverters and their technical solutions.The main content of the paper is as follows:The first part selects the 22nm BSIM4 MOSFET standard device model,and analyzes the CMOS timing fluctuation caused by RDF and the relationship between the doping concentration and the timing change through the industrial HSPICE tool.The results show that the increase in channel doping concentration will cause greater timing deviation of the CMOS inverter from the standard deviation.The second part suppresses the influence of RDF on the timing of CMOS inverters by back-gate bias technology.Firstly,the effect of back-gate voltage on the performance of MOSFET devices is qualitatively observed.Secondly,it compares the standard deviation of the change in timing characteristics of CMOS inverters caused by RDF with or without back gate voltage.The results show that the use of a back gate voltage of V_dd/2 can effectively reduce the timing variations caused by RDF.The third part analyzes the negative capacitance effect of CMOS devices based on Sentaurus TCAD,and explores the influence of negative capacitance effect on circuit timing and power fluctuations caused by RDF.The results show that in the CMOS inverter（NC-CMOS）based on negative capacitance devices,the NC effect can effectively suppress the inverter timing changes caused by the RDF in the channel of the CMOS device.At the same time,the results also show that the average static DC power of NC-CMOS will also decrease as the ferroelectric thickness increases.The work done in this paper not only provides an early prediction for the fluctuation of the timing characteristics of the nano-CMOS inverter,but also proposes a feasible technical solution to suppress the timing fluctuation.