Characterization And Optimization For Low Voltage Design Based On Statistical Static Timing Analysis

In recent years,voltage scaling to sub-threshold(Sub TV)and near-threshold(NTV)domain poses severe challenge to timing analysis and optimization.Firstly,the gate delay becomes non-Gaussian distribution.Meanwhile,performance degradation and uncertainty are increased.These issues cause inapplicability for traditional statistical timing models and sizing strategies.Therefore,accurate modeling of timing distribution and mitigating the impact of performance uncertainty on speed degradation have been deemed as core problem for digital integrated circuits.For the non-gaussian delay distribution issue,several statistical timing models based on log-skew-normal(LSN)distribution are proposed.Meanwhile,the equivalent threshold voltage method and equivalent drain current method are developed.These methods can characterize the timing distribution accurately and solve the multiple random variable issue.For gate sizing strategy in low voltage region,an analytical optimization method for low voltage design through employing worst-case(+3σ)propagation delay as optimization target and deriving the optimal PMOS/NMOS width ratio is proposed.In this thesis,TSMC＿28nm＿HPC+ technology is employed to valiadate the feasibility of proposed statistical models and optimization strategy.For the validation of proposed statistical timing models,several combinational logic gates with single transistor(INV),stack topology(pull-down network of NAND2 cell)and parallel topology(pull-up network of NAND2 cell)are employed.In addition,seven types of combinational logic gates and ISCAS’89 benchmarks are involved in the valiadation of the statistical optimization model.As for the statistical delay distribution model of the standard cells,compared with existing lognormal-distribution-based methods,the error of the mean,variance and percentile point for all of the test gats in this thesis are less than 14.9%.As for the optimization of the standard cells,compared with the two traditional optimization methods based on nominal propagation delay models,synthesis results for ISCAS’89 benchmarks using standard cells designed with the derived optimal size show12.7% enhancement in the worst-case frequent,15.1% reduction in power,and 19.9% reduction in area.