Design And Optimization Of R-LWE Lattice Based Cryptography On Hardware

Advances in the field of quantum computing have threatened the security strength of current and traditional public key cryptography with the rapid development of quantum computer research.Therefore post-quantum cryptography(PQC)has emerged as a new branch of cryptography by focusing on the design of quantum resilient cryptographic algorithms.Among the PQC family,lattice based cryptography(LBC)is one of the most viable alternatives to the classical cryptographic schemes due to its security foundation on worst-case hardness of lattice problems and up-till now is resistant to attacks by the quantum computers.At present,nearly half of encryption schemes in round 2 of national institute of standard and technology(NIST)PQC competition are lattice based.Among the LBC,ring-learning with error(R-LWE)is one of the most studied candidate due to its security,versatility and efficiency.Hence,the research on R-LWE hardware circuit design and its optimization is of great significance for the deployment of PQC schemes in the future.The main work of this thesis is as follows:Firstly,this thesis deeply investigates the theory of R-LWE lattice ciphers and analyzes the security strength of R-LWE scheme along with its decryption failure probability,then evaluates the implementation and optimization techniques for the core modules of R-LWE i.e.the discrete Gaussian sampling and ring polynomial multiplication.In this regards,a lightweight hardware implementation of R-LWE is proposed based on cumulative distribution table(CDT)method for the discrete Gaussian sampling and Schoolbook approach for the ring polynomial multiplication,including a reference model for the entire R-LWE encryption scheme to verify the correctness of the selected algorithm.The proposed implementation achieves the highest frequency with low hardware cost,compared with previous work.Secondly,exploiting the characteristics of discrete Gaussian distribution for the sampling of noise parameters in R-LWE encryption algorithm,two hardware optimization techniques are proposed.The first is the used of signed number convention for the discrete Gaussian data that not only reduced the width of input to the multiplier but also saved hardware resources.This optimization in turn results in efficient utilization of DSP based hardware multipliers by accommodating two multiplications in one DSP without increasing the hardware resources hence greatly improved the hardware efficiency.Thirdly,the number theoretic transform(NTT)based R-LWE hardware design is provided in this work in which the parameters of NTT algorithm are systematically analyzed to design an efficient R-LWE hardware structure by module reusing method.The NTT based R-LWE hardware architecture is presented in time-domain as well in frequency-domain with resource consumption analysis and comparison with previous works.Finally,all the above hardware designs are analyzed and compared based on a proposed weighted unified hardware resource comparison method in which the hardware resources of different designs are converted to equivalent number of slices.The results conclude that the implementation techniques presented in this thesis are efficient in terms of area as well throughput than the available hardware solutions of the same type.