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Research On Optimization Method Of FPGA Design Parameters Based On VTR

Posted on:2021-05-18Degree:MasterType:Thesis
Country:ChinaCandidate:Y H XuFull Text:PDF
GTID:2518306497466734Subject:Software engineering
Abstract/Summary:PDF Full Text Request
The digital circuit design of FPGAs mainly depends on EDA tools because of their increasing scale and complexity.EDA tools reserve many design parameters for engineer.So that circuit designers can have more fine-grained control of the algorithms implemented inside the software and adjust design parameters value to generate a highperformance physical circuit that can be routed.Because the parameter space composed of design parameters is too large and complicated,it is not realistic to explore the parameter space manually.Therefore,researchers have proposed the autotuning method to optimize the design parameters.In this thesis,the design parameter optimization method is studied,and the existing parameter autotuning framework——DATuner is improved.Based on this,a parameter optimization method based on the prior pruning model is proposed,and the evolutionary algorithm is used to support high concurrency and VTR design flow is executed in parallel.The main research work of this thesis is as follows:(1)Since various performance metrics of the circuit are difficult to reach the optimal value at the same time.Optimizing a single performance may not meet the requirements of other performance metrics,resulting in a decline in the overall performance of the circuit.In the existing autotuning framework,only a single performance metric is optimized,resulting in insufficient overall circuit performance.The autotuning algorithm proposed in this thesis uses a heuristic search strategy based on differential evolution to explore the parameter space.Multiple performance metrics of the circuit including power consumption,area and timing is comprehensively considered.(2)In the process of population evolution,the priori pruning model is constructed to predict the routability of design parameters,and the Differential Evolution Based on Prior Pruning(DEBPP)is proposed.A large number of data sets are used to train the priori pruning model,to predict the "routability" of design parameters.Priori pruning is performed when searching the parameter space and infeasible solutions are filtered out,the search efficiency of the parameter space is improved,and tuning time is shortened.(3)To solve the problem of too long program execution time in autotuning,a prediction method based on machine learning is used.According to the existing experimental data set,combined with machine learning algorithms,predict the runtime and performance indicators of the circuit,and filter out the individuals with poor performance and too long runtime during the evolution process.The experimental results show that the tuning performance based on the autotuning method proposed in this thesis has been greatly improved.The tuning time is much reduced compared with the existing autotuning framework DATuner.The fitness of the proposed prior pruning model reaches to more than 97%.
Keywords/Search Tags:FPGA Design, Parameter Optimization, Electronic Design Automation, VTR
PDF Full Text Request
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