Research And Implementation Of Radar Signal Processing System Based On Multi-core DSP

CFAR,target cohesion and single pulse and monopulse angular are the key links in radar signal processing,which can effectively improve the target detection performance of the radar and obtain accurate target spatial position,radial velocity and amplitude information.With the continuous development of radar technology,the real-time,fast and big data processing capabilities of the core processor of the radar signal processing hardware platform have imposed stricter requirements.A high-performance multi-core DSP is the key to achieving the above requirements.This paper combined with a low-altitude detection radar project,researched and implemented the software solution of the radar signal processing system on the multi-core DSP TMS320C6678.The research was carried out in the order from theoretical verification to interface design,multi-core implementation,and finally system debugging.The first is the study of signal processing algorithms.The simulation of the average constant false alarm algorithm is performed.Based on this,the improved average selection method and small selection method are used to effectively eliminate the detection limitations caused by clutter edges and adjacent targets.Contrast and analyze the traditional target aggregation and the new connected domain aggregation algorithm,and give the respective simulation results.The latter is selected to achieve the better aggregation effect and higher efficiency.The calculation formula of single pulse and differential angle measurement is derived and the simulation results are given.Then comes the communication interface research.Develop a set of radar communication schemes to control the radar front-end equipment,achieve high-speed data transmission with FPGA,and display the processed information on the host computer.Provide the driver software design methods for the GPIO,EMIF,SRIO and Gigabit Ethernet interfaces to be used.Complete the network port communication test between the DSP and the terminal,and the SRIO,GPIO,EMIF interface communication test between the DSP and FPGA.Measure the transmission bandwidth of SRIO and network port,and confirm that the communication performance meets the design requirements.Then came the multi-core implementation.Because single-core implementation cannot perform continuous high-speed processing,a multi-core,multi-task,pipeline ping-pong processing software implementation solution based on the SYS/BIOS real-time operating system is proposed.Among them,EDMA is used to move data to save data transmission time.A stable and fast Message Q method is used to complete inter-core communication and to resolve cache consistency issues.Maximizes the use of faster read speed L2 SRAM memory to exchange space,and all cores perform different tasks in parallel.The average utilization of L2 SRAM memory reaches 86%,which is completed every 1.6ms Information reporting.Finally,the entire design is debugged and evaluated for performance.Use the IF radar echo simulator to simulate the echo,debug the initialization,interface,EDMA,signal processing,inter-core communication and other modules.Compare the number of simulated and actual CPI and target information to verify the correctness,stability and accuracy of the entire system.The radar signal processing system studied in this paper meets the requirements of high-speed data processing and has the stability and reliability of continuous operation.It can realize the positioning of radar maneuvering target and lays the foundation for the successful development of the project radar.