Research On Ultra-wideband Miniaturized Frequency-agile Frequency Synthesizer

The frequency synthesizers are the core component of the radar systems and communication systems,with the rapid development of electronic systems,the demand for the frequency synthesizers have become more higher.According to different applications,the demand for indicators of synthesizers are different.The communication systems care more about indicators of phase noise and spurious suppression while radar systems focus more on the frequency switching speed.The phase-locked frequency agility synthesizers having an wideband output,a simple structure,good performance of phase noise performance and spurious suppression among many existing schemes of frequency agility.Therefore,the research on phase-locked agile frequency synthesizers is of great significance.Through the investigation of the literatures,this paper proposes a 2 ～ 15 GHz ultra wideband agile frequency synthesizer based on the already existing research of laboratory on agile frequency synthesizer.Firstly,employing an integrated VCOs of the PLL chip LMX2594 as broadband output scheme,the integrated VCOs can cover frequency from 7.5GHz to 15 GHz,and the output frequency can go below to 10 MHz with channel divider integrated in LMX2594.In order to obtain better characteristics of phase noise and spurious suppression,a method of locking the LMX2594 with an external phase detector HMC698 are adopted,HMC698 possesses ultra low phase noise floor and supports high phase detector frequency and wide loop bandwidth,so the loop bandwidth is determined to be 1MHz,due to the particularity of the phase detector chip,an active 2-order filter is selected as a loop filter.Secondly,in order to achieve frequency resolution as low as 10 k Hz,the output of DDS chip AD9914 is used as the phase detector frequency to drive PLL,for purpose of satisfying high phase detector frequency to drive PLL and suppressing the image frequency of DDS output,437 ～ 545 MHz are selected as the phase detector frequency through frequency plan,then 2.5GHz is chooesd as the reference clock of DDS,this reference clock is produced by step recovery diode frequency multiplier.In order to reduce the lock time of the PLL,the following auxiliary methods are adopted:(1)The frequency presetting method is used to reduce the initial frequency difference.The high speed DAC chip AD9764 is used to preset the initial frequency of VCOs.The maximum presetting error is 69 k Hz,which is far less than the loop bandwidth,it do benefit to achieve fast locking.(2)The method of bypass VCOs calibration is used to switch to the desired output VCO core and frequency band through SPI.It greatly saves the time required for VCOs calibration;(3)The parallel controlled chips are used,such as HMC698,AD9914 and AD9764,saving the time of writing control words compares to serial controlled chips.Based on the system design above,the design of circuit and cavity are processed,and then the circuit is assembled and debugged.After measurement,the frequency hopping time is about15 mirco seconds;The spurious suppression is greater than 50 d Bc;The phase noise is better than-105 d Bc/Hz@100k Hz,the demand of miniaturization is satisfied with the dimension of cavity of 10cm*10cm* 2cm.