Test Set Reordering Method Based On Test Performance Estimation

Since the 1950s,the emergence and vigorous development of integrated circuits,with the development of science and technology,integrated circuit manufacturing technology is more and more exquisite.The internal structure of integrated circuits is becoming more and more complex.More advanced design and technology make the chip have more computing power,but also bring new challenges to the test,a great quantity of test data brings high test cost and longer test time.So a test set reordering method is proposed.The purpose of reordering is to test high value test vectors first,which can ensure the fault coverage and reduce the total detection time.Aiming at the problem of long fault detection time,this dissertation proposes a test vector reordering method based on performance estimation,introduces performance as the standard of test vector reordering,and proposes that performance is the area of the test vector hitting the fault gate.Firstly,the Poisson distribution model of gate area and failure probability is established according to the distribution law of circuit fault.Then,the fault is simulated for the integrated circuit.Then,the fault is injected into each logic gate,and the test vectors obtained by the test generation algorithm are input in turn.The number of times that each test vector hits the fault gate and the gate type are counted by the stop when failure method,The mapping relationship between the test vector and the area of the integrated circuit is established,and then the performance is estimated by using the area of the test vector hitting the fault gate.The performance is regarded as an attribute of the test vector and reordered.For different test vectors,the fault point,fault type and performance of the test are the same,then the reordering process will be combined,So as to reduce the sorted test set.Based on the ISCAS 89 standard circuit,the fault detection time is reduced by 50.85%.Compared with the hierarchical dynamic adjustment test method and the die level adaptive test method,the experimental results show that the proposed method is better.The innovation is that the mapping relationship between the test vector and the area of the integrated circuit is established,and the quality of the test vector is determined by calculating the area of the integrated circuit corresponding to the test vector.The algorithm in this dissertation is based on software and does not need to add any hardware overhead,so it can be directly compatible with the traditional IC test process.