Research On Comprehensive Design Technology Of PIN Limiter

With the development of strong electromagnetic pulse technology,the electromagnetic damage protection of microwave receivers has attracted more and more attention from scholars,especially under the threat of high-power microwave(HPM)electromagnetic environment.Solid-state limiting technology is widely used in radio frequency circuits,and has completed the limiting protection function of input high-power microwave pulses.If the HPM electromagnetic pulse exceeds the maximum withstand power of the limiter,it will cause damage to the receiver’s rear-end low-noise amplifier,mixer and other high-sensitivity devices or even permanent failure.Therefore,low insertion loss,high isolation,high power capacity,and miniaturization have become the development trend of solid-state limiting protection technology.The paper proposes a parallel extended cascade limiter circuit structure based on the conductance modulation effect of PIN diodes.Without significantly increasing the insertion loss of the limiter,the power capacity and isolation of the limiter circuit can be greatly improved.The circuit widens the microstrip line width through a gradual method,which reduces the impedance of the microstrip line and widens the lateral size of the microstrip line,which facilitates the expansion of multiple tubes in parallel,and improves the power capacity of the limiter circuit.Compared with the single-tube cascade mode,the parallel extended cascade limiter circuit has higher power capacity and isolation.Based on the PIN single-tube electro-thermal coupling model,the thermoelectric co-simulation model of the parallel extended cascade limiter circuit is constructed using the circuit simulation software ADS.The junction temperature rise of the PIN diode in the limiter circuit is calculated under different input power conditions.The comparison of the junction temperature rise calculation results of the traditional single-tube cascade limiter circuit and the parallel extended cascade limiter circuit verifies that the latter is in Superiority in power capacity and isolation parameters.Finally,the designed parallel extended cascade limiting circuit was processed and assembled,and the S parameter and 1d B compression point in the small signal state were tested.The insertion loss in the L-band was about 0.18 d B,1.1 GHz～2 GHz S11 is better than-20 d B in the frequency range;an L-band injection experiment platform is built to conduct a high-power pulse test,and the isolation can reach about 30 d B under the condition of 44 d Bm input power.The peak leakage and flat leakage results obtained by the test are basically consistent with the simulation calculation results,which verifies the feasibility of the parallel extended cascade limiter circuit.