Signal Recognition Based On Embedded And Deep Learning

With the world becoming more digital and information,people begin to long for the application of relevant technology in the field of communication system to be more intelligent.In recent years,a large number of deep learning researchers have gradually focused on the fields of military radar communication and satellite navigation,and algorithms such as signal modulation recognition and carrier signal detection based on deep learning have been proposed continuously.However,deep learning algorithms are complex and often time-consuming to compute.In the practical application of relevant technologies,people still hope to implement operations on small,portable,energy-saving and environmental friendly embedded devices,and hope to realize reasoning operation of deep learning algorithms faster on low-power embedded devices.In this paper,embedded devices are taken as the experimental platform and deep network algorithm of signal recognition is taken as the acceleration object to study the acceleration optimization method of deep learning neural network on embedded devices.This paper gives a brief description of the network structure of communication signal recognition network based on deep learning and the principles and structures of various network layers contained in the network.This paper also discusses the feasibility of interlayer parallelism in the deep network of signal recognition to determine the parallelism policy,and then analyzes the parallelism of each network layer in the network.It provides theoretical support for the subsequent parallel network acceleration on embedded devices.In this paper,NVIDIA Jetson TX2,an embedded GPU,was used as an acceleration experimental platform.After studying the parallel acceleration implementation method based on CUDA for this device,the optimization acceleration method of CUDA for NVIDIA GPU was studied in depth.Then,a series of heterogeneous acceleration optimization experiments on the convolution layer of the signal recognition neural network were carried out on TX2.Finally,the optimal acceleration effect was achieved by setting the working group as 256 in a one-dimensional workspace,which was 2.1 times the operation speed of the multi-core processor.Then,heterogeneous parallel acceleration reasoning was carried out on all the network layers of the signal recognition neural network on TX2.In this paper,parallel acceleration and optimization experiments of signal recognition neural network are carried out on DE5-NET,an embedded FPGA device.Open CL,a general heterogeneous parallel framework,is used to complete parallel tasks.Similarly,different optimization methods are used to conduct parallel acceleration optimization experiments on the convolution operation on DE5-NET.The experiment results show that the optimal operation time is 45.882 ms by using the optimization measures of two-dimensional workspace and ten pipeline replication,which is 3.5 times the operation speed of multi-core processor.Besides,all the layers of the whole signal recognition network are placed on DE5-NET for parallel acceleration,which takes60.001 ms and 3.45 times the operation speed of multi-core processor.