Research And Design Of GM-APD Array Readout Circuit For Low Power And Multi-echo Detection

As concepts such as artificial intelligence,autonomous driving,and human behavior recognition are successively proposed,solid-state light detection and ranging(Li DAR)is no longer limited to military and civilian fields such as missile guidance and geological prospecting,and gradually enters the field of commercial consumer products,which makes related applications and needs more extensive.The Flash Li DAR 3D imaging system based on the avalanche photon diode(APD)can realize the reception and recognition of single photon,showing high sensitivity and accuracy.However,with the increase of the array size,higher requirements have been placed on the readout integrated circuit(ROIC)used to detect avalanche current and quantify the time stamp.Miniaturization,low power consumption,and single-pixel multi-echo detection have become research hotspots.This article focuses on the increasing scale of APD arrays and the demand for singlepixel multi-echo detection,and designs a low-power multi-echo detection Geiger mode APD(GM-APD)array readout circuit.Based on low power consumption considerations,except for a few analog circuits that use 5V CMOS devices,the rest use 1.8V CMOS devices.In addition,global clock gating(GCG)is used on the phase-locked loop which only works in the corresponding window,which avoids the start synchronization circuit,streamlines the circuit design,and reduces power consumption;design data readout interface(DRI)which stores and reads quantized data,which adopts shift clock gating(SCG)to avoid redundant readout of shift registers and save power consumption.To achieve multi-echo detection,this paper designs a clock-gated active quenching circuit(AQC)which divides the timing of single photon capture into three states: reset,waiting,quenching,and realizes the three-state cycle through the corresponding timing.This completes the detection of multiple echoes.At the same time,this paper designs a corresponding time-to-digital converter(TDC),which successively quantifies multiple time stamps generated by multi-echo detection.The TDC adopts a combined coarse and fine adjustment architecture,in which a Gray code counter is used for coarse adjustment and an 8-phase clock is used for fine adjustment.To solve the problem of metastable state during TDC sampling,both the counter and 8-phase clock encoding use Gray codes,and the designed dynamic D flip-flop is adopted instead of the traditional D flip-flop.This article also deals with the problem of array non-uniformity initially to ensure that the current gain of arrays is basically the same.Finally,in the pixel layout,try to share the clock,power,bias and other signals,and the pixels are designed back-to-back to reduce the area occupied.Based on the 0.18μm CMOS process,this paper has completed the design of the128×32 GM-APD array readout circuit,and simulated the single-pixel multi-echo detection.At the same time,the TDC range designed in this article is 1μs,and the resolution reaches 500 ps.Finally,the power consumption is compared based on the presence or absence of GCG and SCG.When GCG and SCG are both adopted,the power consumption of the 128×32 pixel readout circuit is reduced from 1368.7m W to 464.6m W.