Application Verification Of Sample Rate Multiplication And Bias Design Of Domestic High Speed ADC

Analog to digital converter plays an important role in data acquisition system.In response to the national demand for domestic IC design,domestic research institutes and chip manufacturers are engaged in the research and development of ADC.However,domestic manufacturers have not enough experience in ADC performance testing and application verification.Therefore,entrusted by a domestic chip manufacturer,our company uses technical experience to conduct pull bias test and application verification for high-performance analog-to-digital conversion chip MBxxxx,On the one hand,the pull bias test can test the performance of ADC more comprehensively,and provide a reference for the compilation of device manual and user use;On the other hand,application verification can provide users with a way to build a high sampling rate data acquisition system using domestic ADC with low sampling rate.The main content of this paper is divided into two parts: application verification and deflection design1、Application verification:First of all,through TIADC technology,two domestic ADC chips with 2GSPS sampling rate are sampled alternately to realize the design of application verification module with 4GSPS sampling rate and 12 bit resolution.T.Including the broadband multi-channel drive circuit design,multi-phase sampling clock circuit design,synchronous reset circuit design,etc;Secondly,receive and process data of high-speed data stream to expand the function of data acquisition module.This paper mainly designs the data deceleration module based on IDDR,and the FIFO data cache module,which completes the functions of data integration the functions of data blending,digital trigger,parallel spot and peak detection are completed to realize the correct display of waveform;Finally,study the method of system error estimation and correction of TIADC system.The three errors of the TIADC system were estimated by sinusoidal fitting algorithm,and the bias,gain and time errors were corrected by a combination of analog correction and digital post-correction.2、Pull off test: First of all,the pull bias circuit is designed according to the range and step of the pull bias of the demand item in the pull bias design board,and the high precision pull bias of the sampling clock,common mode voltage and supply voltage can be realized through the program control way;Then propose the measurement method of ADC performance parameters and measure the performance of ADC in the pull deviation test.The dynamic characteristic parameters and static characteristic parameters of the chip are both tested,and the performance curve of the compatible ADC chip at home and abroad is compared.The experimental results show that after error correction,the sampling rate of the system can reach 4GSPS and the effective bits can reach 9.08 bit,which can meet the requirements of the design index and provide reference for users to design high sampling rate acquisition module;The deviation test method designed in this paper can carry out high precision deviation test with the error range of less than 10% for the demand item,and the recommended working conditions of domestic ADC can be obtained from the performance change curve.In addition,the performance curve comparison of domestic and foreign ADC can help users and manufacturers to further understand the performance of domestic ADC.