Design Of 8-bit Low Power Computing In Memory Circuit Based On RRAM

In recent years,artificial intelligence has made significant progress and has been applied in many areas such as healthcare,education and transportation.However,the huge amount of neural network data brings a new challenge to the intensive data processing capacity of the hardware.Due to the separation of storage units and processing units,the traditional von Neumann structure needs to access data many times,which leads to the "memory wall" problem.In-memory computing solves the data access bottleneck by integrating computing capabilities into the storage units,which is very suitable for high data-density applications such as neural networks.The emergence of new resistive nonvolatile memory(NVRAM)provides the opportunity for realizing lowpower and high-integration in-memory computing.Because the existing design of the in-memory computing core is mainly based on analog computing,Digital to Analog Convertor(DAC)and Analog to Digital Convertor(ADC)interfaces are needed to ensure correct computing function.However,a large number of digital-analog interfaces bring about power consumption and area problems.Moreover,the non-ideal characteristics of nonvolatile memory also severely restrict the precision of the circuit.This thesis first analyzes the architecture design of several existing in-memory computing cores.To solve the above problems in power consumption and precision,we propose a low power in-memory computing core design based on a passive voltage regulator,1R1 T storage unit,and capacitor voltage isolation transistor for better computing energy efficiency and higher linearity.We model Resistive Random Access Memory(RRAM)as the memory cell and analyze the mapping error brought by device inconsistency.A pseudo-binary quantization and bit-line weight mapping method is further proposed to reduce the accuracy loss of the neural network.The circuit simulation shows that the designed memory computing core can achieve the computing power efficiency of 67.26 TOPS/W in an 8-bit pattern.The 8-bit weight array(256*256)consumes only 3.61 m W with a throughput of 242.8 GMACS.The robustness and linearity of the circuit are verified by the Monte Carlo simulation and PVT simulation.The software simulation shows that the algorithm using pseudo-binary quantization and bit-line weight mapping method can reduce the neural network's weight mapping error,thus reducing the decline of accuracy.Experiments show that the proposed algorithm improves the top-1 accuracy by 2.46% and 3.47% on Alex Net and VGG16(ILSVRC2012 dataset),respectively.